标题: 矽化镍在积体电路应用上之材料性质与制程技术
Material Properties and Process Technologies of Nickel Silicide Relevant To VLSI Applications
作者: 王超群
Chao-Chun Wang
陈茂杰
Mao-Chieh Chen
电子研究所
关键字: 矽化镍;浅接面二极体;高温热稳定性;浅接面接触电阻;铜矽化合物;NiSi;shallow junction;thermal stability;contact resistivity;Cu3Si;agglomeration
公开日期: 2004
摘要: 本论文研究主要在于探讨矽化镍在积体电路应用上之材料性质与制程技术。首先,我们探讨矽化镍(NiSi)薄膜的热稳定性。其次,我们探讨以离子植入矽化镍之技术,研制特性极为优越的NiSi/p+n及NiSi/n+p浅接面二极体,并且以四端点凯尔文(Kelvin)结构量测NiSi/p+n结构之接触电阻。最后,对于铜电极接触的TaN/Cu/NiSi/p+n二极体结构的高温稳定性加以探讨。
对于矽化镍(NiSi)薄膜的热稳定性探讨,吾人选定的NiSi薄膜厚度为315及615埃。NiSi薄膜的热稳定性,和离子植入的条件与植入的离子种类有关。我们发现,经过BF2+及氟离子(F+)植入的NiSi薄膜,其热稳定性大为提升,而经过硼离子(B+)及磷离子(P+)植入的NiSi薄膜之热稳定性则显现劣化。NiSi薄膜的热稳定性提升可归因于氟离子可强化NiSi薄膜的键结,进而降低NiSi薄膜与矽基板之间的应力。
其次,我们采用离子植入NiSi层的技术(ITS 方式)配合传统炉管的低温退火以及快速升温退火(RTA)来研制NiSi/p+n和NiSi/n+p浅接面二极体。在本研究中,以传统炉管退火制作的NiSi(310 Å)/p+n浅接面的接面深度介于23到70 nm之间 (自NiSi/Si介面算起)。就600oC 退火30分钟所形成的NiSi/p+n接面而言,接面深度为56 nm,顺向电流理想因素可达1.01,在5伏逆向偏压下之接面漏电流密度可低于2 nA/cm2。以RTA退火制作的NiSi(310 Å)/p+n浅接面的接面深度介于23到56 nm之间。就650oC RTA (30秒)退火所形成的NiSi/p+n接面而言,接面深度为37 nm,顺向电流理想因素可达1.001,在5伏逆向偏压之接面漏电流密度可低于4 nA/cm2。另外,我们制作四端点凯尔文(Kelvin)结构,据以量测NiSi/p+n接触的接触电阻。量测结果显示,NiSi/p+n接触电阻率小于1 μΩ-cm2,符合未来对小面积欧姆接触之要求。
对NiSi/n+p浅接面的研制,吾人使用的NiSi薄膜厚度为615 Å。以磷离子(P+)及氟离子(F+)作双重布植,再经过750oC退火90分钟所得之NiSi/n+p浅接面,接面深度为71 nm,顺向电流理想因素可达1.08,在5伏逆向偏压下之接面漏电流密度可低于1 nA/cm2。植入氟离子可以提升NiSi的高温稳定性,并且有效改善矽化镍与矽基板间的界面平整度,进而改善接面特性。
对于TaN/NiSi/p+n 接面二极体而言,其特性并不因500oC的炉管退火30分钟而有所改变。但是对于铜电极接触的TaN/Cu/NiSi(310 Å)/p+n接面二极体,接面特性能够忍受的退火温度仅及350oC;退火温度超过350oC,则接面特性开始呈现劣化。经由SIMS分析显示,Cu在375oC时开始穿入NiSi,导致接面劣化,逆向偏压漏电流增加。此外,在425oC的高温退火可使Cu3Si矽化物相迅速增长,从而导致TaN层的破裂以及TaN/Cu/NiSi/Si 结构的解体。
This dissertation studies the basic material properties and process technologies of nickel silicide relevant to VLSI applications. First, the thermal stability of nickel monosilicide (NiSi) is investigated, including the effect of fluorine atoms incorporation in the NiSi film. Second, high performance NiSi/p+n and NiSi/n+p shallow junctions formed by ITS scheme followed by low temperature furnace annealing and RTA process are investigated. In addition, contact resistance of the NiSi/p+n junction is measured using a four-terminal Kelvin structure. Finally, we also investigate the thermal stability of the Cu-electrode contacted TaN/Cu/NiSi/p+n shallow junctions.
Thin NiSi silicide films of 315- and 615-Å thicknesses on Si substrate were used to investigate the thermal stability of NiSi films. It was found that the thermal stability of the NiSi film is dependent on the implant species and the implantation condition. Both BF2+ and F+ implantations could improve the NiSi film’s thermal stability, while B+ and P+ implantations might result in degrading the thermal stability. In the system of NiSi/Si, the implanted fluorine atoms are presumably segregated to the NiSi grain boundaries and NiSi/Si interface, forming the strong Si–F and Ni–F bonds, and thus suppressing NiSi film agglomeration by decreasing the interfacial energy, i.e. stress between the NiSi layer and the Si substrate; as a result, the integrity of the silicide layer is preserved at high temperatures.
The NiSi/p+n shallow junctions were fabricated using ITS scheme by BF2+ implantation into/through NiSi(310 Å)/Si samples followed by low temperature furnace annealing (FA) or RTA process. For the FA NiSi/p+n junction diodes fabricated in this work, the junction depth ranges from 23 to 70 nm measured from the NiSi/Si interface. The reverse bias current density of less than 2 nA/cm2 can be easily achieved; specifically, the NiSi(310 Å)/p+n junction fabricated with a 35keV BF2+ implantation to a dose of 5×1015 cm-2 followed by a 30-min-FA at 600oC, has a forward ideality factor of 1.01, a reverse bias current density (at –5 V) of less than 1 nA/cm2, and a junction depth of 56nm. For the RTA NiSi/p+n junction diodes fabricated in this work, the junction depth ranges from 23 to 56 nm measured from the NiSi/Si interface. The reverse bias current density of lower than 4nA/cm2 can be easily achieved; specifically, the NiSi(310 Å)/p+n junction fabricated with a 35keV BF2+ implantation to a dose of 5×1015 cm-2 followed by a 30-sec-RTA at 650oC, has a forward ideality factor of 1.001, a reverse bias current density (at –5 V) of 0.6 nA/cm2, and a junction depth of 37 nm. The contact resistance of the NiSi-contacted p+n junction fabricated using ITS scheme is measured by four terminal Kelvin test structure. The NiSi/p+n contact fabricated with BF2+ implantation at 35 keV to a dose of 5×1015 cm-2 through a 310Å-thick NiSi followed by 700 to 750oC RTA exhibited a contact resistivity (ρc) of about 0.05 μΩ-cm2. This low value contact resistivity is able to meet the requirement for future VLSI applications
A P+/F+ dual implantation (P+ implant followed by F+ implant) is designed to promote the high temperature thermal stability of the NiSi film for the formation of NiSi/n+p shallow junctions. The NiSi(615Å)/n+p junction fabricated with P+/F+ dual implantation at 35/30 keV to a dose of 5×1015/5×1015 cm-2 followed by a 90min thermal annealing at 750oC, has a forward ideality factor of 1.08, a reverse bias current density (at 5 V) of 0.7 nA/cm2, and a junction depth of 71 nm. The additional F+ implantation was able to improve the NiSi/Si interface morphology at high temperatures, which is beneficial to the formation of high performance NiSi/n+p shallow junctions.
The TaN/NiSi/p+n junction diode was found to be thermally stable up to at least 500oC (by a 30 min thermal annealing). However, the Cu contacted TaN/Cu/NiSi(310 Å)/p+n junction diode remained stable only up to a temperature of 350oC. SIMS analysis indicates that Cu started to penetrate into the NiSi-contacted shallow junction when the sample was annealed at 375oC, leading to a drastic increase in reverse bias leakage current. The rapid growth of Cu3Si silicide phase during the thermal annealing at 425oC resulted in the break of TaN cover layer, causing the eventual collapse of the TaN/Cu/NiSi/Si structure.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT008811808
http://hdl.handle.net/11536/53557
显示于类别:Thesis


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