深次微米SOI元件相關特性之研究

Abstract

在這篇論文裡,利用模擬研究在SOI(Silicon on Insulator)結構下 的0.1um nMOSFET元件之特性,其目的在為未來深次微米SOI元件設計及製 造提供一個參考.我們可由結果看出臨界電壓與矽膜厚度間的關係及其隨 不同摻雜濃度變數的變化.另外,研究中亦顯示了加入負的 Interface - Fixed - Charge可降低 subthreshold swing , 並提高臨界電壓( threshold voltage) 的值, 因此有助於減少漏電流的產生.最後, 我們針 對SOI的不足提出改進的方法. The device design considerations of 0.1um nMOSFET in SOI (Silicon on Insulator) structure , are proposed by simulation in this thesis. The purposeof this study is to provide the reference for future design and process of the deep - submicron SOI device. We can see the threshold voltage dependence onthe silicon film thickness and variant doping concentration. Besides, this study shows the effect of interface fixed - charge. The negative interface fixed-charge not only reduce the subthreshold swing (S.S.), but also increase the threshold voltage; as a result, the off leakage current can be decreased. Finally, we provide some suggestions to improve the characteristics of the device.