標題: A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
作者: Wong, Cheng-Chi
Tang, Cheng-Hao
Lai, Ming-Wei
Zheng, Yan-Xiu
Lin, Chien-Ching
Chang, Hsie-Chia
Lee, Chen-Yi
Su, Yu-T.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.
URI: http://hdl.handle.net/11536/6523
ISBN: 978-1-4244-0786-6
期刊: PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE
起始頁: 273
結束頁: 276
Appears in Collections:Conferences Paper