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dc.contributor.author李敬贊en_US
dc.contributor.authorChing-Tsan Leeen_US
dc.contributor.author李崇仁en_US
dc.contributor.authorChung-Len Leeen_US
dc.date.accessioned2014-12-12T02:23:12Z-
dc.date.available2014-12-12T02:23:12Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880428060en_US
dc.identifier.urihttp://hdl.handle.net/11536/65698-
dc.description.abstract鎖相迴路常應用於數位或通訊系統中為時序訊號產生器,它決定了整個系統的穩定度。在此篇論文中,我們提出了一個特徵式的雜訊模型, 藉由數學工具的使用,推導出轉移函式,以討論在鎖相迴路中各部份電路的電源雜訊對輸出頻率的影響;然後,我們以CMOS製程設計一個電路,以SPICE作驗證,並分別在不同的地方給予不同頻率的雜訊,將SPICE 模擬出來的結果和數學推導的結果作比較以驗証我們的模型。結果顯示我們提出的模型,可以適切的應用於分析雜訊;如此可節省分析鎖相迴路電路雜訊影響的計算時間,並提供建議給電路的設計者。zh_TW
dc.description.abstractThe Phase-Locked Loop circuit is usually employed as a clock generator in the digital or communication system. Its stability determines the limiting stability of system. In this thesis ,we propose a behavioral noise model for which the transfer function was deduces by mathematics tools (MatLab). Based on this model , the power supply noises injected from each sub-block of the PLL circuit were analyzed to see how they affect the PLL output frequency ( jitter) . A practical PLL circuit was designed by using the TSMC 0.6u CMOS process. For this circuit ,noise of various frequencies were injected to each sub-block of the PLL .The spice simulation results were compared with those derived from the model .It showed that the spice experimental result agree with those derived from the model .This demonstrates that our proposed mathematical model can be used to analyze noise of the PLL circuit, enabling saving of much computation time. 英文摘要...…………………………………………………………………………………...II 目錄………………………………………………………………………………………….III 圖片索引……………………………………………………………………………………..V 表格索引…………………………………………………………………………………...VII 第一章 簡介……………………………………………………. ………………………….1 1.1 頻率分析對一個時序產生器的重要性……………………………………………..1 1.2 鎖相迴路的特性模型………………………………………………………………..1 1.3 來自鎖相迴路各部份的雜訊源對系統穩定度的影響……………………………..2 1.4 頻率(相位)分析的前置工作………………………………………………………...2 1.5論文的大綱…………………………………………………………………………...3 第二章 一個相位(頻率)分析的特徵模型…. ……………………………………………..4 2.1 Jitter參數的定義…..…………..…………………………………………………….4. 2.1.1 週期的變動(Period Jitter) ……………………………………………………..4 2.1.2 長期的週期變動 (Long-Term Jitter) ...…………………………………….…5 2.1.3 週期對週期的變動(Cycle-to-Cycle Jitter) ……………………………….…...5 2.2鎖相迴路的方塊圖…………………………………..………………………………6 2.2.1頻率變動(Jitter)和相位錯誤的累積……………..…………………………….7 2.2.2 壓控振盪器的特徵模型………………………….……………………………8 2.2.3 相位頻率偵測器的特型模型…………………….…………………………..10 2.2.4 電荷幫浦(Charge Pump)…...…………………….…………………………..10 2.2.5 低通濾波器(Low Pass Filter) ……………..…………………………………11 2.2.6 由模型推導出關係式………………………………………………………...11 第三章 實際電路作驗証………………………………………………………………….13 3.1 實際電路的範例……………………………………………………………………13 3.1.1 數位相位檢測器(Digital Phase Detector) …………………………………..13 3.1.2 電荷幫浦及低通濾波器(Charge Pump and LPF) …………………………..14 3.1.3 壓控振盪器(Voltage Control Oscillator) ……………………………………14 3 .2 參數的粹取……………………………………………………………………….15 3.2.1 壓控振盪器的參數…………………………………………………………….15 3.2.2 數位相位檢測器的參數Kd…………………………………………………...17 3.2.3 低通濾波器的參數…………………………………………………………….17 3.3 MatLab模擬的實際結果……………………………………………………………18 3.4 實際電路的雜訊影響分析…………………………………………………………19 3.4.1 由電荷幫浦及低通濾器來的雜訊對鎖相迴路的影響……………………...20 3.4.2 壓控振盪器的雜訊對鎖相迴路的影響……………………………………...21 3.5 實驗結果和模型的比較和討論……………………………………………………21 3.5.1 相同性的討論………………………………………………………………...21 3.5.2 相異性的討論………………………………………………………………...22 第四章 結論………………………………………………………………………………...23en_US
dc.language.isozh_TWen_US
dc.subject鎖相迴路zh_TW
dc.subject雜訊zh_TW
dc.subject電源zh_TW
dc.subject接地zh_TW
dc.subjectPLLen_US
dc.subjectnoiseen_US
dc.subjectpoweren_US
dc.subjectgrounden_US
dc.title鎖相迴路中的雜訊對頻率漂移影響之研究zh_TW
dc.titleJitter Analysis Due to Noise in the Phase-Locked Loop Circuitsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis