矽鍺製程之低漏電流二極體串聯電路及其在靜電放電防護上之應用

Abstract

本篇論文主旨在設計適用於矽鍺製程之靜電放電防護電路。所提出的新型電路可以有效地降低二極體串產生的漏電流問題，且具有高的靜電放電防護能力。本篇論文分為三大部分，透過實驗的量測以及理論的推導來驗證所提出的新型設計。 第一部分是在0.35微米矽鍺製程中，藉由改變元件結構以及佈局參數來探討二極體與矽鍺異質接面雙極性電晶體之靜電放電防護能力，並利用傳輸線觸波產生器來量測這些元件在高能量電流脈衝注入下的電壓電流特性。此外，也探討在低壓，高壓及高速等不同應用之矽鍺異質接面雙極性電晶體，其靜電放電防護能力。 因為寄生元件的存在，傳統的二極體串將會產生嚴重的基極漏電流問題，尤其是在高溫的狀態下。本論文在第二部份是針對矽鍺製程中設計出新型的二極體，並使用新型的二極體組成低漏電流二極體串聯電路。本設計配合適當的電路技巧可有效地降低二極體串造成的漏電流問題。此外，本設計是利用二極體串在順偏導通狀態下導去靜電放電電流，因此在小的佈局面積下就具有高的靜電放電耐受度。 針對第二部份所提出的低漏電流二極體串聯電路作為靜電放電箝制電路，為了達到此電路具有最低漏電流的目的，第三部分藉由推導此電路寄生元件的特性方程式以及模擬結果來達到電路設計參數的最佳化，再經由實驗的量測來驗證此結果。本論文更進一步提出第二種新型的二極體串，從理論推導及實驗結果證明其漏電流將更有效地被降低。此外，使用此新型二極體串作為矽鍺異質接面雙極性電晶體之觸發電路也在本論文中被提出與驗證。 在本論文中，已經針對於矽鍺製程中設計出低漏電且高靜電放電耐受度之二極體串聯電路，其適用於積體電路之靜電放電箝制電路。所設計的靜電放電防護電路均已在實際晶片上成功驗證，並有數篇會議論文發表。

The aim in this thesis is to design the ESD protection circuits in SiGe BiCMOS process. In this design, the leakage current of the diode string can be effectively reduced and a high ESD robustness can be achieved. There are three parts in this thesis. The first part investigates the ESD robustness of the diodes and heterojunction bipolar transistors (HBTs) by different device structures and layout parameters. The transmission line pulse generator (TLPG) is also used to investigate the characteristics of these devices under high-current stress. In addition, the ESD robustness of HBTs for low-voltage, high-voltage, and high-speed applications are also investigated. For the traditional diode string, the parasitic p-n-p bipolar junction transistor (BJT) devices in the diode string will induce a large leakage current into the substrate, especially under high temperature condition. In the second part, a new diode structure in SiGe process is proposed and low-leakage-current diode string (LLCDS) is formed by this new diode structure. Furthermore, the leakage current of LLCDS can be effectively reduced by extra circuit design. Because the diode string is designed to sustain the ESD stress under forward-biased condition, a high ESD robustness can be achieved in a small silicon layout area. In the third part, the optimum design on the circuit to minimize the leakage current of LLCDS as the power-rail ESD clamp circuit is evaluated by calculating the physical formulas of the parasitic devices in the diode string and the simulation results. The experimental results are also performed to verify the simulation results. Furthermore, the second design on the diode string as the power-rail ESD clamp circuit is proposed to further reduce the leakage current. In addition, the power-rail ESD clamp circuit with new diode string as the trigger circuit of HBT is also proposed and verified. In summary, LLCDS as the power-rail ESD clamp circuit are developed in SiGe process with low leakage current and high ESD robustness. Each of the design has been successfully verified in the testchips and also published in the international conference papers.