整體非同步局部同步系統之介面電路設計及其應用於快速傅利葉轉換架構

Abstract

本論文對於整體同步局部非同步系統使用交握協定和非同步先進先出暫存器來實現介面電路設計並且應用於快速傅利葉轉換架構。在非同步包裹裡，一個新的可停止時脈控制器、寫埠和讀埠被提出，資料可安全地傳輸於不同操作時脈頻率下之相鄰包裹。爲了要增加傳送模組端的產能運算效能，非同步先進先出暫存器被加入於兩相鄰模組間。一個使用些微修正Muller C元件之非同步先進先出暫存器單元被提出來減低交握電路的複雜度。這架構有低功率、低延遲時間及可重複使用的特性。根據TSMC 0.13 1P8M CMOS技術，佈局對於4個、8個、16個先進先出暫存器被實現出來。

結合整體同步局部非同步設計和雙電壓系統應用於十六點radix-22單路徑延遲回授之快速傅利葉轉換架構，這個架構被分成三個包裹，每一個包裹有各自的時脈頻率和操作電壓。包裹形成的介面是由準位轉換器修正過後的交握電路和非同步先進先出暫存器所實現出來。在TSMC 0.13um技術下，模擬結果顯示比較於十六點整體同步單電源電壓之快速傅利葉轉換架構，以整體同步局部非同步設計為根基且雙電源電壓之快速傅利葉轉換架構減少30%的功率消耗且減少25.5%延遲時間。這些技術在未來的單系統晶片將會被廣泛的使用。

The interface circuit designs using handshake protocols and asynchronous first-in-first-out (FIFO) for globally-asynchronous locally-synchronous (GALS) systems are realized and apply to the Fast Fourier Transform Architecture in this thesis. A new pausible clock controller, write-port and read-port in asynchronous wrappers are proposed and data items can be transferred safely through adjacent wrappers operating at different clock frequencies. To increase the efficiency of throughput at the sender’s module, the asynchronous FIFO is inserted between two adjacent modules. An asynchronous FIFO cell is proposed to reduce the complexity of the handshake circuits by using Muller C element with some modifications. It has the properties of being low power, low latency and reusable. The physical layouts for the FIFO sizes of four, eight and sixteen are implemented based on the TSMC 0.13um 1P8M CMOS technology.

The GALS design combined with dual-supply systems is applied to the 16-point radix-22 single-path delay feedback FFT architecture. The architecture is divided into three wrappers and each wrapper has its own local clock frequency and supply voltage. The interfaces formed from wrappers are implemented by handshake circuits and asynchronous FIFO, which are modified with level converters. Simulation results in TSMC 0.13um technology shows that the 16-point GALS-based FFT architecture in dual supply voltages has 30% power savings and 25.5% latency reduction compared to the globally-synchronous one in single supply voltage. These techniques will be widely used in the future systems-on-a-chip (SOC) design.