低功率濾波之研究

Abstract

本論文提出一種新的反轉極性的方法，來實現一個低功率的乘法器，文中討論各種實現電路的方式，並實作一個低功率的乘法器電路來跟其它種實現方式比較。接下來並討論應用單一個乘法在各種濾波架構下時，此乘法器的優缺點，以及改進的方式。在同一種濾波架構下，再考慮多個乘法器在電路上、運算時序上的編排方式，以達到應用此乘法器時最低功率的效果

In this thesis, we propose a new multiplier design technique using inverse polarity method for low-power filtering. The new design can reduce signal switching activity within a multiplier array. We also investigate various implementation techniques for the realization of low-power multipliers. The new designed results are compared to the existing ones. In addition, we investigate the advantages and disadvantages of using a single multiplier of different kinds, assuming various kinds of filter structures. On the other hand, for each structure, we consider the resource allocation and scheduling for best low-power effect using the new multiplier.