| 標題: | Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT |
| 作者: | Lin, S. H. Cheng, C. H. Chen, W. B. Yeh, F. S. Chin, Albert 機械工程學系 電子工程學系及電子研究所 Department of Mechanical Engineering Department of Electronics Engineering and Institute of Electronics |
| 關鍵字: | LaTiO;low V(t);solid-phase diffusion (SPD) |
| 公開日期: | 1-Sep-2009 |
| 摘要: | In this letter, we report a low threshold voltage (VI) of 0.12 V in self-aligned gate-first TaN/LaTiO n-MOSFETs, at an equivalent oxide thickness of only 0.63 run. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Sb that reduced the high-kappa dielectric interfacial reactions. |
| URI: | http://dx.doi.org/10.1109/LED.2009.2027723 http://hdl.handle.net/11536/6730 |
| ISSN: | 0741-3106 |
| DOI: | 10.1109/LED.2009.2027723 |
| 期刊: | IEEE ELECTRON DEVICE LETTERS |
| Volume: | 30 |
| Issue: | 9 |
| 起始頁: | 999 |
| 結束頁: | 1001 |
| Appears in Collections: | Articles |
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- Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions / Lin, S. H.;Cheng, C. H.;Chen, W. B.;Yeh, F. S.;Chin, Albert
- Low-V-t TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions / Lin, S. H.;Liu, S. L.;Yeh, F. S.;Chin, Albert
- Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack / Cheng, C. H.;Chou, K. I.;Chin, Albert
- Low-V(t) TaN/HfLaO n-MOSFETs Using Low-Temperature Formed Source-Drain Junctions / Lin, S. H.;Liu, S. L.;Yeh, F. S.;Chin, Albert
- 低臨界電壓雙金屬閘極金氧半電晶體製作技術之研發 / 鄭存甫;荊鳳德
- Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack / Cheng, C. H.;Chou, K. I.;Chin, A.
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