1.25GHz ,8個相位輸出之全數位鎖相迴路

Abstract

隨著網路資料傳輸速度的與日遽增，低成本高速串列式傳輸技術亦隨之蓬勃發展。串列式傳送器的應用相當廣，可應用於光纖網路、萬用串列匯流排(USB)、IEEE-1394等系統。本論文探討使用0.18微米CMOS製程來實現傳送器前端之相關電路技術，其具體目的在達成1.25Gbps的串列式全數位化傳送器電路。 在此論文中，我們有兩個研究主題。首先，我們分析並比較各個種類的多工器。依據比較結果與IEEE802.3ah的規格要求，我們以全數位化方式來實現10對1的多工器。此外，我們將此多工器和鎖相迴路、輸出驅動器整合在一起成為一個完整的串列式資料傳輸器。此電路設計採用0.18um 1P6M TSMC CMOS製程技術實現。經由量測結果，其抖動值約為66ps，並可達到1.25Gbps的傳輸速度，晶片面積為1900*990um2 。 第二個研究主題為1.25GHz全數位鎖相迴路，我們提出一個具有高解析度多相位輸出的數位控制震盪器電路。接著我們藉由MATLAB simulink來對整個系統作功能驗證, 並且得到可接受的輸出抖動對應到的解析度大小。此電路設計採用0.18um 1P6M TSMC CMOS製程技術實現。佈局完成後經由SPICE模擬得到輸出抖動為104ps，功率消耗為24.49毫瓦，晶片面積為880*730um2。

The increasing demand for the data bandwidth in network has driven the development of high-speed serial link technology. The high speed serial links have been applied in optical communication, USB, IEEE-1394. This thesis develops a transmitter front-end circuit design in 0.18um CMOS process technologies. The objective goal of this research is to realize 1.25Gbps an all-digital serial link transmitter. There are two major topics in this thesis. First, we compare and analyze all types of serializer. Base on the comparison results and IEEE802.3ah specification, we implement a 10 to 1 serializer in all-digital approach. Besides, we integrate this serializer, PLL, and output driver together to become a complete serial link data transmitter. It has been implemented using 0.18um 1P6M TSMC CMOS technology. The measured jitter is about 66ps and can be capable of operate 1.25Gbps data rate. Chip size is about 1900*990um2. The second research topic is a 1.25GHz all digital phase-locked loop. We propose a high resolution digitally-controlled oscillator with multi-phase output. Functional verification of the ADPLL is performed by MATLAB simulink and gets optimal DCO resolution corresponding to output clock jitter acceptable. It will be implemented using 0.18um 1P6M TSMC CMOS technology. The output clock jitter is about 104ps after post-layout simulation, and power consumption is about 24.49mW. Overall chip size is about 880*730um2 .