標題: Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
作者: Chen, Jung-Sheng
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Gate-tunneling leakage;loop filter;MOS capacitor;phase-locked loop (PLL)
公開日期: 1-Aug-2009
摘要: In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.
URI: http://dx.doi.org/10.1109/TED.2009.2022696
http://hdl.handle.net/11536/6903
ISSN: 0018-9383
DOI: 10.1109/TED.2009.2022696
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 56
Issue: 8
起始頁: 1774
結束頁: 1779
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