A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

Abstract

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mV(PP) to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 mu m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm(2).