Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions

doi:10.1109/LED.2009.2020307

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DC 欄位	值	語言
dc.contributor.author	Lin, S. H.	en_US
dc.contributor.author	Cheng, C. H.	en_US
dc.contributor.author	Chen, W. B.	en_US
dc.contributor.author	Yeh, F. S.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.date.accessioned	2014-12-08T15:09:23Z	-
dc.date.available	2014-12-08T15:09:23Z	-
dc.date.issued	2009-06-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2009.2020307	en_US
dc.identifier.uri	http://hdl.handle.net/11536/7162	-
dc.description.abstract	We demonstrate a low threshold voltage (V,) of -0.17 V and good hole mobility (54 cm(2)/V (.) s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.	en_US
dc.language.iso	en_US	en_US
dc.subject	LaTiO	en_US
dc.subject	low V(t)	en_US
dc.subject	solid-phase diffusion (SPD)	en_US
dc.title	Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2009.2020307	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	30	en_US
dc.citation.issue	6	en_US
dc.citation.spage	681	en_US
dc.citation.epage	683	en_US
dc.contributor.department	機械工程學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Mechanical Engineering	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000266409200032	-
dc.citation.woscount	2	-
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