標題: 單線傳輸介面設計
The Single-Wire Interface Design
作者: 何承振
Ho, Chen-Cheng
蘇朝琴
Su, Chau-Chin
電控工程研究所
關鍵字: 單線介面;鎖相迴路;全數位時脈資料回復;數位控制震盪器;頻率偵測器;Single-Wire Interface;Phase-Locked Loop;All Digital Clock Data Recovery;Digital-Controlled Oscillator;Frequency Detector
公開日期: 2013
摘要: 在本篇論文我們提出了一個應用於單線通訊系統的傳輸介面,在此傳輸系統中,主電路利用單一傳輸線串接所有子電路,而電路運作過程中,主電路利用此傳輸線對子電路充電同時傳送資料,當子電路充電完畢後會開始執行主電路所要求的命令,最後再利用此傳輸線做資料的回傳,在整個資料傳輸系統中為單一傳輸線,因此子電路利用整流與穩壓方式將線上電壓轉換成可用的直流電源。 所提出的單線傳輸設計使用TSMC 0.18um 1P6M標準CMOS製程來實現,整體輸入電壓為1.8V,子電路內部使用穩壓電路產生穩定1V供整體電路使用,系統操作速度為1MHz,傳輸使用單一導線來完成,子電路內使用一個外接電容儲能,整個傳輸介面電路晶片面積為0.86*1.12mm2。
In this paper, an interface for single-wire communication is proposed. In the system, the master uses one wire to connect to all slaves. The master charges slaves and transfers data to them by using a single wire. When the energy in slave circuit is enough to operate, it executes the command being received. Finally the slave transfers the results back by using the same wire. The overall system uses only one wire so the rectifier and regulator are designed in the slaves. The slave uses a rectifier and a regulator circuit to store energy in an off-chip capacitor and generate a stable supply voltage for the internal circuits. The single-wire interface is implemented in TSMC 0.18um 1P6M standard CMOS process. The operation voltage of master circuit is 1.8V and the slave use regulator to generate a stable 1V for the internal circuits. Operation frequency of overall system is 1MHz and data is transmitted at 1Mbps. The chip area is 0.86 1.12mm2.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079912525
http://hdl.handle.net/11536/73665
Appears in Collections:Thesis


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