低耗電量非同步嵌入式處理器SA8051設計與實作

Abstract

隨著製程的進步，FPGA (可規劃的邏輯陣列) 可以容納越來越多的邏輯閘，目前已經可以將整個電腦系統實作在單一的FPGA晶片上，而soft-core的處理器正是系統的核心，所謂的soft-core處理器是指用硬體描述語言設計，經過合成後可實作在可重複規劃的設備中，例如：FPGA。 8051是最流行的微控制器並且可被用在低耗電量的產品中，因此，我們以英特爾8051指令集的架構為基礎，設計一個低耗電量的非同步8051處理器，稱作SA8051。我們使用Balsa工具來實作SA8051，Balsa是一個以CSP (Communication Sequential Process)為基礎的非同步電路硬體描述語言並且可以合成非同步電路。Balsa可以合成適用於Xilinx合成器的Verilog netlist。我們目前已經將SA8051實作於Xilinx FPGA Spartan-IIE 300 ft256 。我們比較的對象是沒有使用gated clock的同步8051，實驗結果顯示，在動態耗電量方面，大約是同步版本的三分之一。 為了節省面積，我們不使用Balsa來合成記憶體，而是直接使用FPGA裡面的區塊記憶體來做為SA8051的程式與資料記憶體，然而，FPGA的區塊記憶體是同步電路而SA8051卻是非同步電路，因此，在記憶體與處理器間必須藉由一個交握的介面做溝通。

Recent advancements in Field Programmable Gate Array (FPGA) technology have resulted in FPGA devices that support the implementation of a complete computer system on a single FPGA chip. A soft-core processor is a central component of such a system. A soft-core processor is a microprocessor defined in software, which can be synthesized in programmable hardware, such as FPGAs. 8051 is the most popular microcontroller and hence is often used in applications where low energy consumption is important. The 8051 soft-core processor from Intel Corporation is studied and a Verilog netlist of the 8051 soft-core has been developed, called SA8051. The SA8051 is a low-power asynchronous processor modeled by Balsa which is a CSP-based asynchronous hardware description language and synthesis tool. A Verilog netlist for XST (Xilinx Synthesis Tool) is generated by Balsa. We implement SA8051 in Xilinx FPGA Spartan-IIE 300 ft256. We compare SA8051 with the synchronous 8051 without gated clock. The SA8051 shows a dynamic power advantage of a factor 3 compared to the synchronous implementation. In order to reduce area cost, we do not model ROM and RAM of the SA8051 by Balsa. We use Block RAM in FPGA chip as program memory and data memory. The interface between the synchronous memory and the asynchronous processor is designed.