用於UWB之CORDIC based 等化器設計

Abstract

本論文提出以CORDIC為核心的IEEE802.15.3a接收器為設計目標的等化器設計與實現。並利用平行化及管線化(pipeline)結構，設計出具有高速以及低複雜度的等化器，其輸出量最快可達到655百萬取樣。為了能完成完整的UWB模擬及研究。我們根據S-V通道模型，以及Intel提出的室內通道模型，建構出UWB所需的通道模型。在演算法方面，以CORDIC為核心的通道估測演算法，以及通道估測誤差修補演算法被推導出，並驗證其複雜度低於一般的演算法。同時,在CMOS.18製程下以SYNOSYS ASTRO完成macro設計。

In this thesis, we proposed a high speed Equalizer for CORDIC based inner receiver, including modulation, FFT/IFFT, synchronization and equalization. By the parallel and pipeline design, the proposed design, based on the specification of IEEE 802.15.3a Ultra Wideband system, has good speed performance and low complexity. The throughput can achieves 655M samples per second. In order to fully simulation the UWB system, a channel model base on S-V model and Intel proposed channel model are built and verification. We proposed a CORDIC based channel estimation and channel estimation error tracking algorithm with low computation complexity. Also, the macro design in CMOS.18μm with core size 1470 x 1470 um2 is applied with SYNOPSYS ASTRO