一低複雜度無線區域網路Viterbi解碼器之設計與實作

Abstract

近幾年來無線區域網路被廣範使用並快速的普及, 維特比 (Viterbi) 解碼器是大家耳熟能詳的解碼方法,它在基頻接收器中扮演非常重要的角色, 維特比演算法可以採用軟決策(soft decision)或是硬決策(hard decision)的做法來實現, 軟決策的做法可以得到較佳的解碼效能但是需要較複雜的運算能力, 在某些無線網路的應用中並不嚴苛要求效能,此時硬決策便可以滿足系統的要求。在本論文中,我們考慮設計並實現一個無線網路中使用硬決策的維特比解碼器,我們提出一個加權硬決策的做法,此做法可以有效提升硬決策維特比解碼器的效能並且享有硬決策的簡易運算的優點,另外我們使用預測追蹤法來有效降低記憶體使用頻率, 如此可降低約20%的電源損耗,最後我們使用高階硬體描述語言(VHDL)來模擬探討我們的設計並且用可程式化邏輯陣列(FPGA)加以實現

The wireless local area network (WLAN) has been widely used in recent years. The Viterbi decoder, a well-known decoding scheme, plays an important role in the baseband receiver. The Viterbi algorithm can be implemented as soft-decision or hard-decision. The soft-decision Viterbi algorithm has better performance but requires higher computational complexity. In some WLAN applications, the performance requirement is not stringent. In this case, the hard-decision decoding algorithm can be sufficient. In this thesis, we consider the design and implementation of a hard-decision WLAN Viterbi decoder. We propose a hard-decision weighting scheme that can effectively enhance the conventional hard-decision Viterbi decoder while remains the inherent low complexity property. We also use a trace back prediction method that can reduce the memory access frequency during the trace back operation. This can reduce the power consumption of the whole decoder up to 20%. Finally, we use VHDL to model the designed decoder and implement it using an FPGA.