高介電常數介電質於金屬-絕緣層-金屬電容之電性研究

Abstract

隨著元件尺寸的減縮，閘極厚度必須降低以維持電容值和驅動電流。由國際半導體技術藍圖，我們知道在1.5奈米製程以下，降低介電質厚度將使得漏電流呈指數級增加。然而，高介電常數介電質的應用將是一種有效防止漏電流呈指數級增加的可能解決方法。 在本篇論文中，我們研究使用高介電常數介電質的金屬－絕緣體－金屬電容。高電容密度、低電容電壓係數、低漏電流和簡單單一介電質製作都是使用此高介電常數介電質（TiTaO）之優點。 藉由使用高介電常數介電質（TiTaO）和高功函數的銥電極，我們達成滿足國際半導體技術藍圖所需求性能的高性能金屬－絕緣體－金屬電容。

With the scale-down of device size, the gate thickness has to decrease to maintain the capacitance value and drive current levels. By ITRS, we know that decreasing dielectric thickness will increase the leakage current exponentially below 1.5 nm. However, high-k materials are much preferred as a possible solution that prevent the exponential increase of the gate leakage current. In this thesis, we study the metal-insulator-metal capacitors using high-k dielectrics. The high capacitance density, low voltage coefficients of capacitance, low leakage current and simple single dielectric process are the merits using the novel high-k TiTaO dielectric. By using the high-k TiTaO dielectric an1d the high work-function Ir electrode, we have exhibited a high performance MIM capacitor that meets the ITRS roadmap requirements for analog capacitors.