以TSMC CMOS-0.35μm 製程設計一電容式感測器電路

Abstract

在許多應用中, 電容式感應器為有著高精確度與可實行的感應器中的一種。一般而言, 電容式感測器電路包含著一個電容電壓轉換器與類比數位轉換器。其中電容電壓轉換器被直接的與感應器相連接, 且用來放大感應器的感應訊號; 接著, 電容電壓轉換器的輸出訊號被一類比數位轉換器所量化以獲得數位化的資料,以便於運用在複雜的數位訊號處理上。本論文設計了一個包含電容電壓轉換器與三角積分調變器(或稱三角積分類比數位轉換器) 的電容式感應器電路;該電路不止是保持著簡單性而且也符合12位元解析度要求。

一直以來電容電壓轉換器與積分三角調變器兩者皆需要一個含有輸出共模回授能力的全差動在放大器,我們將共模回授差動對中的電晶體以體極驅動方式來設計該放大器。我們更進一步的設計將該共模回授的差動對操作在次臨界區。由此, 該差動放大器能有著較高的輸出訊號範圍。我們實行了將參數在三個標準差的變化量下的模擬且得到了在供應電壓Vdd: 3.3 V 時共模電壓為1.63∼1.67 V。在這樣的選擇與設計讓共模回授對於元件不匹配達到強健的設計,使得輸出操作電壓維持在Vdd/2:1.65 V 附近。

在積分三角調變器中, 我們提出了一個新的架構去實現取樣與加法功能。我們稱之為電容分享技術。這樣的技術使得已被發展完善的積分三角調變器能免於由取樣電容的不匹配或者輸入訊號的共模電壓漂移造成的影響而降低電路性能。

該電容式感應器在1 MHz 的時脈下被量測。感應器的容值變化可達60 fF 與1 KHz 的頻寬。在正弦波改變量為42 fF 與頻率為869 Hz 的變化下, 電容電壓轉換器達到了74 dB 的訊號雜訊失真比; 在相同的測試條件下, 積分三角調變器獲得了80.5 dB 的訊號雜訊失真比。因此, 該感應器電路有著12位元的解析度。此電容感測器電路面積為1.5 (mm)^2且在供應電壓為3.3 V 時, 整個系統的消耗功率為2.4 mW。

Capacitive sensor is one of highly accurate and easible sensors in many applications. Capacitive sensor circuit, in general, consists a capacitance to voltage converter (CV-C) and an analog to digital converter (ADC). CV-C is connected directly with the sensor and served to amplify the sense signal of sensor; its output signal is then quantized by ADC to yield digital data so that sophisticated digital signal processing algorithms can be applied. This thesis designs a capacitive sensor circuit which consists a CV-C and a Sigma-Delta Modulator(SDM, or called Sigma-Delta ADC); the circuit not only keeps the simplicity but also meets the resolution of 12-bits.

Since both CV-C and SDM need a fully differential amplifier with output common-mode feedback (CMFB) capability, we use bulk-driven transistors in CMFB differential pairs to design the amplifier. We further design the CFMB differential pairs operate in the subthreshold region. Hence, the obtained differential amplifier can have a higher output signal swing. We perform simulations with the 3 sigma parameter variations and obtain the common-mode voltage of 1.63~1.67 V for supply voltage Vdd: 3.3 V. This choice and design make the CMFB robust to device mismatch such that the output operating voltages remains at about Vdd/2.

In the SDM, we propose a new configuration to realize the functions of both sampling and addition. We call it the capacitor-sharing technique. This technique makes the developed SDM immune to degrade the circuit performance from either sampling capacitance mismatch or the variation of common mode voltage of input signals.

The final capacitive sensor is measured using 1 MHz clock. It can measure the capacitance variation of sensor up to 60 fF and the bandwidth 1 KHz. Individually, the CV-C achieves 74 dB SNDR at 42 fF sine wave variation with frequency 869 Hz; at the same test condition, the SDM obtains 80.5 dB SNDR. Hence, the total resolution of the sensor circuit is 12-bits. The power consumption of the whole system is 2.4 mW at a 3.3 V supply voltage and the chip area is 1.5 (mm)^2.