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公開日期標題作者
2013A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-AssistChang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loopChuang, Li-Pu; Chang, Ming-Hung; Huang, Po-Tsang; Kan, Chih-Hao; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITIONHuang, Yu-Chieh; Huang, Po-Tsang; Hu, Yu-Chen; Wu, Shang-Lin; You, Yan-Huei; Wang, Yung-Kuei; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chen, Kuan-Neng; Chuang, Ching-Te; Chiou, Jin-Chern; 生物科技學系; 電機工程學系; 電控工程研究所; 國際半導體學院; Department of Biological Science and Technology; Department of Electrical and Computer Engineering; Institute of Electrical and Control Engineering; International College of Semiconductor Technology
1-二月-2011A 65 nm 0.165 fJ/Bit/Search 256 x 144 TCAM Macro Design for IPv6 Lookup TablesHuang, Po-Tsang; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007A 65nm low power 2T1D embedded DRAM with leakage current reductionChang, Mu-Tien; Huang, Po-Tsang; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009An Adaptive Congestion-Aware Routing Algorithm for Mesh Network-on-Chip PlatformHuang, Po-Tsang; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2011Adaptive Power Control Technique on Power-Gated CircuitriesHsieh, Wei-Chih; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2017An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing MicrosystemHu, Yu-Chen; Huang, Yu-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chang, Hsiao-Chun; Yang, Yu-Tao; You, Yan-Huei; Chen, Jr-Ming; Huang, Yan-Yu; Lin, Yen-Han; Duann, Jeng-Ren; Chiu, Tzai-Wen; Hwang, Wei; Chuang, Ching-Te; Chiou, Jin-Chern; Chen, Kuan-Neng; 生物科技學系; 電子工程學系及電子研究所; 電控工程研究所; Department of Biological Science and Technology; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
1-六月-2012All Digital Linear Voltage Regulator for Super- to Near-Threshold OperationHsieh, Wei-Chih; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple ReductionKuo, Yi-Ping; Huang, Po-Tsang; Wu, Chung-Shiang; Liang, Yu-Jie; Chuang, Ching-Te; Chu, Yuan-Hua; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC ApplicationsWu, Chung-Shiang; Lin, Kai-Chun; Kuo, Yi-Ping; Chen, Po-Hung; Chu, Yuan-Hua; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing ApplicationChen, Jr-Ming; Huang, Po-Tsang; Wu, Shang-Lin; Hwang, Wei; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing ApplicationsHuang, Teng-Chieh; Huang, Po-Tsang; Wu, Shang-Lin; Chen, Kuan-Neng; Chiou, Jin-Chern; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
3-五月-2007Asynchronous first-in first-out cellChu, Yeh-Lin; Hwang, Wei
24-七月-2008BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBYHuang, Po-Tsang; Hwang, Wei; Chang, Shu-Wei
5-七月-2007Clock switching circuitWu, Jian-Hua; Hwang, Wei
2008A controllable low-power dual-port embedded SRAM for DSP processorYang, Hao-I; Chang, Ming-Hung; Lin, Tay-Jyi; Ou, Shih-Hao; Deng, Siang-Sen; Liu, Chih-Wei; Hwang, Wei; 電子與資訊研究中心; Microelectronics and Information Systems Research Center
2015Custom 6-R, 2-or 4-W Multi-Port Register Files in an ASIC SOC with a DVFS Window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS TechnologyHsieh, Henry; Dhong, Sang H.; Lin, Cheng-Chung; Kuo, Ming-Zhang; Tseng, Kuo-Feng; Yang, Ping-Lin; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2012Design and Iso-Area V-min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOSChang, Ming-Hung; Chiu, Yi-Te; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Design of memory sub-system in H.264/AVC decoderLi, Chih-Hung; Chang, Chang-Hsuan; Peng, Wen-Hsiao; Hwang, Wei; Chiang, Tihao; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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