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公開日期標題作者
20093D 65nm CMOS with 320 degrees C Microwave Dopant ActivationLee, Yao-Jen; Lu, Yu-Lun; Hsueh, Fu-Kuo; Huang, Kuo-Chin; Wan, Chia-Chen; Cheng, Tz-Yen; Han, Ming-Hung; Kowalski, Jeff M.; Kowalski, Jeff E.; Heh, Dawei; Chuang, Hsi-Ta; Li, Yiming; Chao, Tien-Sheng; Wu, Ching-Yi; Yang, Fu-Liang; 電子物理學系; 電子工程學系及電子研究所; 電信工程研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics; Institute of Communications Engineering
28-十月-2014Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM applicationChin, Fun-Tat; Lin, Yu-Hsien; You, Hsin-Chiang; Yang, Wen-Luh; Lin, Li-Min; Hsiao, Yu-Ping; Ko, Chum-Min; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2013Al-SiO2-Y2O3-SiO2-poly-Si Thin-Film Transistor Nonvolatile Memory Incorporating a Y2O3 Charge Trapping LayerPan, Tung-Ming; Yen, Li-Chen; Mondal, Somnath; Lo, Chieh-Ting; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-七月-2011Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave AnnealingHsueh, Fu-Kuo; Lee, Yao-Jen; Lin, Kun-Lin; Current, Michael I.; Wu, Ching-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-四月-2010Benefit of NMOS by Compressive SiN as Stress Memorization Technique and Its MechanismLiao, Chia-Chun; Chiang, Tsung-Yu; Lin, Min-Chen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-四月-2011Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film TransistorsMa, William Cheng-Yu; Chiang, Tsung-Yu; Yeh, Chi-Ruei; Chao, Tien-Sheng; Lei, Tan-Fu; 電機工程學系; Department of Electrical and Computer Engineering
1-八月-2013Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film TransistorsChen, Kun-Ming; Tsai, Tzu-I; Lin, Ting-Yao; Lin, Horng-Chih; Chao, Tien-Sheng; Huang, Guo-Wei; Huang, Tiao-Yuan; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-十二月-2008Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface TreatmentMa, Ming-Wen; Chiang, Tsung-Yu; Wu, Woei-Cherng; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
14-八月-2019Characteristics of In0.7Ga0.3As MOS Capacitors Obtained using Hydrochloric Acid Treatment, Ammonium Sulfide Passivation, Methanol Treatment, and Forming Gas AnnealingChung, Sheng-Ti; Huang, Yi-Chin; Fu, Yen-Chun; Lee, Yao-Jen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2010The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate StructureKuo, Po-Yi; Huang, Yan-Syue; Lue, Yi-Hsien; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電機工程學系; Department of Electrophysics; Department of Electrical and Computer Engineering
1-二月-2008Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectricMa, Ming-Wen; Chen, Chih-Yang; Su, Chun-Jung; Wu, Woei-Cherng; Wu, Yi-Hong; Kao, Kuo-Hsing; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-一月-2020Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas AnnealingChung, Sheng-Ti; Lee, Yao-Jen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-五月-2007Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratioKuo, Po-Yi; Chao, Tien-Sheng; Hsieh, Pei-Shan; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-八月-2010Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon NanocrystalsChiang, Tsung-Yu; Wu, Yi-Hong; Ma, William Cheng-Yu; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Yang, Wen-Luh; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-四月-2011Characterization of Enhanced Stress Memorization Technique on nMOSFETs by Multiple Strain-Gate EngineeringLu, Tsung-Yi; Chang, Tien-Shun; Huang, Shih-An; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2014Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave AnnealWu, Chien-Ting; Lee, Yao-Jen; Hsueh, Fu-Kuo; Sung, Po-Jung; Cho, Ta-Chun; Current, Michael Ira; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-七月-2017Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETsHsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
2015Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch TechnologyLee, Yao-Jen; Hou, Fu-Ju; Chuang, Shang-Shiun; Hsueh, Fu-Kuo; Kao, Kuo-Hsing; Sung, Po-Jung; Yuan, Wei-You; Yao, Jay-Yi; Lu, Yu-Chi; Lin, Kun-Lin; Wu, Chien-Ting; Chen, Hisu-Chih; Chen, Bo-Yuan; Huang, Guo-Wei; Chen, Henry J. H.; Li, Jiun-Yun; Li, Yiming; Samukawa, Seiji; Chao, Tien-Sheng; Tseng, Tseung-Yuen; Wu, Wen-Fa; Hou, Tuo-Hung; Yeh, Wen-Kuan; 電子物理學系; 電機學院; 電子工程學系及電子研究所; Department of Electrophysics; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-二月-2020Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETsLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-十二月-2014Effect of Sensing Film Thickness on Sensing Characteristics of Dual-Gate Poly-Si Ion-Sensitive Field-Effect-TransistorsYen, Li-Chen; Tang, Ming-Tsyr; Tan, Chia-Ying; Pan, Tung-Ming; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
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