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公開日期標題作者
1-二月-1999A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detectorJiang, HC; Wu, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2003Active device under bond pad to save I/O layout for high-pin-count SOCKer, MD; Peng, JJ; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC'sKer, MD; Jiang, HC; Peng, JJ; Shieh, TL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998The BJT-based silicon-retina sensory system for direction- and velocity-selective sensingJiang, HC; Wu, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuitsKer, MD; Jiang, HC; Chang, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS processKer, MD; Chang, CY; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2001Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technologyKer, MD; Jiang, HC; Chang, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001ESD test methods on integrated circuits: An overviewKer, MD; Peng, JH; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solutionKer, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering
1-六月-1999An improved BJT-based silicon retina with tunable image smoothing capabilityWu, CY; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2001In the blink of a silicon eyeCheng, CH; Wu, CY; Sheu, B; Lin, LJ; Huang, KH; Jiang, HC; Yen, WC; Hsiao, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuitsPeng, JJ; Ker, MD; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC'sKer, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering
2001Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnologyKer, MD; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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