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公開日期標題作者
1-八月-2000ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2000An automatic controller extractor for HDL descriptions at the RTLLiu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Automatic functional vector generation using the interacting FSM modelLiu, CNJ; Yen, CC; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2003Automatic interconnection rectification for SoC design verification based on the port order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003An automatic interconnection rectification technique for SoC design integrationWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2002An automorphic approach to verification pattern generation for SoC design verification using port-order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996BDD based lambda set selection in Roth-Karp decomposition for LUT architectureJiang, JH; Jou, JY; Huang, JD; Wei, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-八月-2002Bootstrap Monte Carlo with adaptive stratification for power estimationHuang, HL; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998Compatible class encoding in hyper-function decomposition for FPGA synthesisJiang, JHR; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2001Converter-free multiple-voltage scaling techniques for low-power CMOS digital designYeh, YJ; Kuo, SY; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2000Crosstalk-driven interconnect optimization by simultaneous gate and wire sizingJiang, IHR; Chang, YW; Jou, JY; 資訊工程學系; 電子工程學系及電子研究所; Department of Computer Science; Department of Electronics Engineering and Institute of Electronics
1-十二月-2000Delay-optimal technology mapping for hard-wired non-homogeneous FPGAsChuang, HH; Jou, JY; Shung, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2003A design-for-verification technique for functional pattern reductionLiu, CNJ; Chen, IL; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2004A divide-and-conquer-based algorithm for automatic simulation vector generationYen, CC; Jou, JY; Chen, KC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Effective error diagnosis for RTL designs in HDLSJiang, TY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003An efficient approach for error diagnosis in HDL designShi, CH; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004An efficient approach for hierarchical submodule extractionLin, YW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2001Efficient coverage analysis metric for HDL design validationLiu, CN; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001An efficient design-for-verification technique for HDLsLiu, CNJ; Chen, IL; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2005An efficient heterogeneous tree multiplexer synthesis techniqueHuang, HW; Wang, CY; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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