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1-一月-2018Back-Channel Etched Double Layer In-W-O/In-W-Zn-O Thin-Film TransistorsLi, Zhen-Hao; Kuo, Po-Yi; Chen, Wen-Tzu; Liu, Po-Tsun; 光電工程學系; Department of Photonics
2010The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate StructureKuo, Po-Yi; Huang, Yan-Syue; Lue, Yi-Hsien; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電機工程學系; Department of Electrophysics; Department of Electrical and Computer Engineering
1-五月-2007Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratioKuo, Po-Yi; Chao, Tien-Sheng; Hsieh, Pei-Shan; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-八月-2010Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon NanocrystalsChiang, Tsung-Yu; Wu, Yi-Hong; Ma, William Cheng-Yu; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Yang, Wen-Luh; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-七月-2017Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETsHsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
30-八月-2018Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stackRuan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kuo, Po-Yi; Yu, Min-Chin; Kan, Kai-Zhi; Chien, Ta-Chun; Chen, Yi-Heng; Sze, Simon M.; 電子工程學系及電子研究所; 光電工程學系; 光電工程研究所; Department of Electronics Engineering and Institute of Electronics; Department of Photonics; Institute of EO Enginerring
1-二月-2020Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETsLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-一月-2018Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film TransistorsLiu, Po-Tsun; Chang, Chih-Hsiang; Kuo, Po-Yi; Chen, Po-Wen; 光電工程學系; Department of Photonics
1-一月-2019Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-十一月-2019Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
2016Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC ApplicationsHsieh, Don-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-一月-2018High Mobility Tungsten-Doped Thin-Film Transistor on Polyimide Substrate with Low Temperature ProcessRuan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Yu, Min-Chin; Gan, Kai-jhih; Chien, Ta-Chun; Kuo, Po-Yi; Sze, Simon M.; 電子工程學系及電子研究所; 光電工程學系; 顯示科技研究所; Department of Electronics Engineering and Institute of Electronics; Department of Photonics; Institute of Display
1-一月-2018High Performance Amorphous In-W-Zn-O Thin Film Transistor with Ultra-Thin Active Channel for Low Voltage OperationLiu, Po-Tsun; Kuo, Po-Yi; Hsu, Shan-Ming; 光電工程學系; 光電工程研究所; Department of Photonics; Institute of EO Enginerring
1-十一月-2014High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETsKuo, Po-Yi; Lu, Yi-Hsien; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
十一月-2016High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FETHsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2011High-Performance Poly-Si TFTs of Top-Gate with High-kappa Metal-Gate Combine the Laser Annealed Channel and Glass SubstrateLu, Yi-Hsien; Chien, Chao-Hsin; Kuo, Po-Yi; Yang, Ming-Jui; Lin, Hsiao-Yi; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-二月-2012High-Performance Poly-Si Thin-Film Transistors With L-Fin ChannelsLu, Yi-Hsien; Kuo, Po-Yi; Lin, Je-Wei; Wu, Yi-Hong; Chen, Yi-Hsuan; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
二月-2017High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization techniqueHsieh, Dong-Ru; Kuo, Po-Yi; Lin, Jer-Yi; Chen, Yi-Hsuan; Chang, Tien-Shun; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
1-十月-2006The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETsYou, Hsin-Chiang; Kuo, Po-Yi; Ko, Fu-Hsiang; Chao, Tien-Sheng; Lei, Tan-Fu; 材料科學與工程學系奈米科技碩博班; 電子物理學系; 電子工程學系及電子研究所; Graduate Program of Nanotechnology , Department of Materials Science and Engineering; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
2015Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold SwingKuo, Po-Yi; Lin, Jer-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
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