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公開日期標題作者
1-八月-2004Annealing effect on boron high-energy-ion-implantation-induced defects inHsu, WC; Liang, MS; Chen, SC; Chen, MC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Barrier characteristics of PECVD alpha-SiC : H dielectricsChiang, CC; Wu, ZC; Wu, WH; Chen, MC; Ko, CC; Chen, HP; Jeng, SM; Jang, SM; Yu, CH; Liang, MS; 電子物理學系; Department of Electrophysics
1-六月-2001Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETsYang, KN; Huang, HT; Chen, MJ; Lin, YM; Yu, MC; Jang, SM; Yu, DCH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2001Characterization of hot-hole injection induced SILC and related disturbs in flash memoriesYih, CM; Ho, ZH; Liang, MS; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Comparative study of physical and electrical characteristics of F- and C-doped low-K CVD oxidesWu, ZC; Shiung, ZW; Chiang, CC; Wu, WH; Chen, MC; Jeng, SM; Chang, W; Chou, PF; Jang, SM; Yu, CH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2000Detection of the defects induced by boron high-energy ion implantation of siliconHsu, WC; Chen, MC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2001Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLKWu, ZC; Shiung, ZW; Wu, RG; Liu, YL; Wu, WH; Tsui, BY; Chen, MC; Chang, W; Chou, PF; Jang, SM; Hu, CH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETsYang, KN; Huang, HT; Chen, MJ; Lin, YM; Yu, MC; Jang, SM; Yu, CH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2001Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETsYang, KN; Huang, HT; Chen, MJ; Lin, YM; Yu, MC; Jang, SSM; Yu, DCH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Effects of base oxide in HfSiO/SiO2 high-k gate stacksWu, WH; Chen, MC; Wang, MF; Hou, TH; Yao, LG; Jin, Y; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2005Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacksWu, WH; Chen, MC; Tsui, BY; How, YT; Yao, LG; Jin, Y; Tao, HJ; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2005Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacksWu, WH; Chen, MC; Tsui, BY; How, YT; Yao, LG; Jin, Y; Tao, HJ; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2004Effects of O-2- and N-2-plasma treatments on copper surfaceChiang, CC; Chen, MC; Li, LJ; Wu, ZC; Jang, SM; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2000Effects of polysilicon gate doping concentration on plasma charging damage in ultrathin gate oxidesChen, CC; Lin, HC; Chang, CY; Huang, TY; Chien, CH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Electrical reliability issues of integrating low-K dielectrics with Cu metallizationWu, ZC; Shiung, ZW; Wang, CC; Fang, KL; Wu, RG; Liu, YL; Tsui, BY; Chen, MC; Chang, W; Chou, PF; Jang, SM; Yu, CH; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2001Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization designLee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2001Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk modelsLee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2006HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicideWu, CH; Hung, BF; Chin, A; Wang, SJ; Yen, FY; Hou, YT; Jin, Y; Tao, HJ; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technologyChung, SS; Yeh, CH; Feng, SJ; Lai, CS; Yang, JJ; Chen, CC; Jin, Y; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2006Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stackChung, SS; Yeh, CH; Feng, HJ; Lai, CS; Yang, JJ; Chen, CC; Jin, Y; Chen, SC; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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