國立陽明交通大學機構典藏：瀏覽交通大學機構典藏

瀏覽的方式：作者 Peng, JJ

顯示 1 到 9 筆資料，總共 9 筆

公開日期	標題	作者
1-一月-2003	Active device under bond pad to save I/O layout for high-pin-count SOC	Ker, MD; Peng, JJ; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001	Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's	Ker, MD; Jiang, HC; Peng, JJ; Shieh, TL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003	Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits	Ker, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
1-十月-2003	ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness	Ker, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
2002	Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution	Ker, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering
1-六月-2002	Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs	Ker, MD; Peng, JJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002	Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits	Peng, JJ; Ker, MD; Jiang, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-十一月-2002	Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology	Ker, MD; Hsu, HC; Peng, JJ; 電機學院; College of Electrical and Computer Engineering
2003	Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's	Ker, MD; Peng, JJ; Jiang, HC; 電機學院; College of Electrical and Computer Engineering

顯示 1 到 9 筆資料，總共 9 筆