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公開日期標題作者
1995A 1.5 V CMOS balanced differential switched-capacitor filter with internal clock boostersWU, CY; WEY, WS; YU, TC; 電機學院; College of Electrical and Computer Engineering
1995A 1.5 v CMOS current-mode cyclic analog-to-digital converter with digital error correctionCHEN, CC; WU, CY; CHO, JJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1994A 10-B 225-MHZ CMOS DIGITAL-TO-ANALOG CONVERTER (DAC) WITH THRESHOLD-VOLTAGE COMPENSATED CURRENT SOURCESCHIN, SY; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1995A 2-D ANALYTIC MODEL FOR THE THRESHOLD-VOLTAGE OF FULLY DEPLETED SHORT GATE-LENGTH SI-SOI MESFETSHOU, CS; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995A 3-V 1-GHz low-noise bandpass amplifierWU, CY; HSIAO, SY; LIU, RY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1985AN ACCURATE AND ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SMALL-GEOMETRY MOSFETS WITH SINGLE-CHANNEL ION-IMPLANTATION IN VLSIWU, CY; HUANG, GS; CHEN, HH; TSENG, FC; SHIH, CT; 工學院; College of Engineering
1-十二月-1985AN ACCURATE MOBILITY MODEL FOR THE I-V-CHARACTERISTICS OF N-CHANNEL ENHANCEMENT-MODE MOSFETS WITH SINGLE-CHANNEL BORON IMPLANTATIONWU, CY; DAIH, YW; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1994AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLECHIN, SY; WU, CY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-1993ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGICWU, CY; CHENG, KH; WANG, JS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-1987THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGICWU, CY; WANG, JS; TSAI, MK; 電控工程研究所; Institute of Electrical and Control Engineering
1-十月-1989ANALYSIS AND MODELING OF INITIAL DELAY TIME AND ITS IMPACT ON PROPAGATION DELAY OF CMOS LOGIC GATESYANG, YH; WU, CY; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
1980AN ANALYSIS AND THE FABRICATION TECHNOLOGY OF THE LAMBDA BIPOLAR-TRANSISTORWU, CY; 電控工程研究所; 奈米中心; Institute of Electrical and Control Engineering; Nano Facility Center
1984AN ANALYTIC AND ACCURATE MODEL FOR THE THRESHOLD VOLTAGE OF SHORT CHANNEL MOSFETS IN VLSIWU, CY; YANG, SY; CHEN, HH; TSENG, FC; SHIH, CT; 電控工程研究所; Institute of Electrical and Control Engineering
1-六月-1987AN ANALYTIC IV MODEL FOR LIGHTLY DOPED DRAIN (LDD) MOSFET DEVICESHUANG, GS; WU, CY; 交大名義發表; 工學院; National Chiao Tung University; College of Engineering
1-七月-1990AN ANALYTIC SATURATION MODEL FOR DRAIN AND SUBSTRATE CURRENTS OF CONVENTIONAL AND LDD MOSFETSHUANG, GS; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-四月-1986AN ANALYTIC THRESHOLD-VOLTAGE MODEL FOR SHORT-CHANNEL ENHANCEMENT MODE N-CHANNEL MOSFETS WITH DOUBLE BORON CHANNEL IMPLANTATIONWU, CY; HUANG, GS; CHEN, HH; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1981AN ANALYTICAL MODEL FOR HIGH-LOW-EMITTER (HLE) SOLAR-CELLS IN CONCENTRATED SUNLIGHTSHEN, WZ; WU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1981BARRIER HEIGHT ENHANCEMENT OF THE SCHOTTKY-BARRIER DIODE USING A THIN UNIFORMLY-DOPED SURFACE-LAYERWU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1980BARRIER HEIGHT REDUCTION OF THE SCHOTTKY-BARRIER DIODE USING A THIN HIGHLY DOPED SURFACE-LAYERWU, CY; 電控工程研究所; 奈米中心; Institute of Electrical and Control Engineering; Nano Facility Center
1981THE BIAS-DEPENDENT PHOTOELECTRIC BARRIER HEIGHT OF THE SCHOTTKY DIODESWU, CY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
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