標題: | Power gating technique for embedded pseudo SRAM |
作者: | Cheng, Ching-Yun Chang, Ming-Hung Hwang, Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2007 |
摘要: | In this paper, we deploy power gating technique on a lowpower Pseudo SRAM circuit with 3TID gain cell. A 256word x 32-BL-pair 3TID gain cell array is implemented in standard logic technology with TSMC 0. l3urn model f6r multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3TID gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC I 00nm technology model). |
URI: | http://hdl.handle.net/11536/12257 http://dx.doi.org/10.1109/ICICIC.2007.522 |
ISBN: | 978-1-4244-0582-4 |
DOI: | 10.1109/ICICIC.2007.522 |
期刊: | 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers |
起始頁: | 260 |
結束頁: | 263 |
顯示於類別: | 會議論文 |