Power gating technique for embedded pseudo SRAM

Abstract

In this paper, we deploy power gating technique on a lowpower Pseudo SRAM circuit with 3TID gain cell. A 256word x 32-BL-pair 3TID gain cell array is implemented in standard logic technology with TSMC 0. l3urn model f6r multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3TID gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC I 00nm technology model).