標題: | A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression |
作者: | Su, Ming-Chiuan Chen, Wei-Zen Wu, Pei-Si Chen, Yu-Hsiang Lee, Chao-Cheng Jou, Shyh-Jye 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Burst-mode clock and data recovery (BMCDR);gated-VCO (GVCO);gigabit passive optical network (GPON);phase-locked loop (PLL) |
公開日期: | 1-Mar-2015 |
摘要: | A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI(pp) jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps(rms). The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm(2) only. It dissipates 12.4 mW from 1 V supply. |
URI: | http://dx.doi.org/10.1109/TCSI.2014.2367573 http://hdl.handle.net/11536/124554 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2014.2367573 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 62 |
起始頁: | 743 |
結束頁: | 751 |
Appears in Collections: | Articles |