標題: Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process
作者: Dai, Chia-Tsen
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Double-diffused drain (DDD);latchup;n-buried layer (NBL)
公開日期: 六月-2016
摘要: The optimization of guard ring structures to improve latchup immunity in an 18 V double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has together been investigated in a silicon test chip. The layout parameters including the anode-to-cathode spacing and the guard ring width are also studied to seek their impacts on latchup immunity. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity. The suggested guard ring structures can be applied to the high-voltage circuits in this 18 V DDDMOS process to meet the new Joint Electron Device Engineering Council standard (JESD78D) with the trigger current of over +/- 200 mA.
URI: http://dx.doi.org/10.1109/TED.2016.2549598
http://hdl.handle.net/11536/133947
ISSN: 0018-9383
DOI: 10.1109/TED.2016.2549598
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 63
Issue: 6
起始頁: 2449
結束頁: 2454
顯示於類別:期刊論文