具有多層P/N 3D結構通道 之高度微縮60奈米短通道無接面場效電晶體

Abstract

此論文延續本實驗室團隊開發之混合式P/N通道無接面電晶體，以此結構為基準，再往上增加一層混合式P/N通道，成為多層混合式P/N通道無接面場效型電晶體，混合式P/N通道中的N型基板提供了P/N接面的空乏區，等效通道厚度變薄，通道的物理厚度可以增加，降低通道製程之困難度，提升元件導通電流，並藉由多層空乏區增進閘極控制能力提升元件電性。 論文中比較混合式P/N與多層混合式P/N通道結構多晶矽無接面場效電晶體。多層混合式P/N通道的新穎結構展現了極佳的電特性，舉例來說：超陡峭之次臨界擺幅(subthreshold swing, SS)值為 77 mV/dec、極低的汲極引致能障下降(drain-induced barrier lowering, DIBL)值為3.58 mV/V、較高的開關電流比(Ion/Ioff ratio >108)。當兩種通道結構皆微縮成短通道的電晶體，多層混合式P/N通道皆較混合式P/N通道有較輕微的短通道效應，不論是汲極偏壓在線性區與飽和區下的電性結果，都具有一致的趨勢。 在溫度改變的情況下，多層混合式P/N通道結構相對於單層混合式P/N通道結構在臨界電壓，導通電流(On state current, I¬on)，漏電流(Off state current, Ioff)，次臨界擺幅等電性參數對溫度的變化皆較穩定，當電晶體操作在攝氏125度的情況下，其電導(trans-conductance, gm)值亦不易隨著閘極電壓增加而減少，再次驗證多層混合式P/N通道結構的優越特性，因此多層的混合式P/N通道結構之多晶矽無接面場效電晶體在低功率消耗、系統級晶圓及系統級封裝之應用有極佳的潛在優勢。 多層混合式P/N通道無接面場效型電晶體如此良好的電性與簡易的製程，未來在三維堆疊積體電路應用上有極高的發展希望。

In this dissertation, we introduce a multi-hybrid P/N junctionless field effect transistor (FET) which comes from a hybrid P/N channel proposed by our laboratory previously. The hybrid P/N channel is composed of a P+ channel and an N+ silicon layer. The depletion layer between P+ channel and N+ substrate may reduce the effective thickness of the P type channel.[1, 2] This idea may not only overcome the constraint of the channel thickness on a junctionless device, but also improve the on state current of the junctionless device.[1] Furthermore, the performance of the device was promoted by the multi-layer stacking.[3] The multi-hybrid P/N junctionless field effect transistor was demonstrated with a polycrystalline silicon technology. The fabricated devices show excellent electrical characteristics in terms of steep subthreshold swing (SS = 77 mV/dec), negligible drain-induced barrier lowering (DIBL = 3.58mV/V), high on-off current ratio (Ion/Ioff > 108). If we compare with hybrid P/N and multi-hybrid P/N junctionless device, we find that the performance of multi-hybrid P/N junctionless device is better than hybrid P/N junctionless device. When the two channel structure is fabricated as short channel devices, the multi-hybrid P/N junctionless device has less influence of short channel effects (SCEs) than hybrid P/N junctionless device. No matter the drain voltage is bias at linear region or saturation region, it keeps the same trend that the multi-hybrid P/N junctionless devices have excellent performance. In temperature dependence measurement, the multi-hybrid P/N junctionless device shows the better stability of the temperature variation. The trans-conductance of multi-hybrid P/N junction device degenerates slowly under high gate overdrive even when it is operated at high temperature as 125 degree Celsius. Those results reconfirmed the trend that the performance of multi-hybrid P/N junctionless device is better than hybrid P/N junctionless device. The feature makes the scheme potential for low power circuits, System-on-Chip (SoC) and power management system applications.[3] The good characteristics of multi-hybrid P/N junctionless device enable this approach promising for three dimensional stacked integrated circuits applications in the near future