標題: Layout-Based Dual-Cell-Aware Tests
作者: Wu, Tse-Wei
Lee, Dong-Zhen
Wu, Kai-Chiang
Huang, Yu-Hao
Chen, Ying-Yen
Chen, Po-Lin
Chern, Mason
Lee, Jih-Nung
Kao, Shu-Yi
Chao, Mango C. -T.
資訊工程學系
電子工程學系及電子研究所
Department of Computer Science
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2019
摘要: Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.
URI: http://hdl.handle.net/11536/152981
ISBN: 978-1-7281-1170-4
ISSN: 1093-0167
期刊: 2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS)
起始頁: 0
結束頁: 0
Appears in Collections:Conferences Paper