標題: ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
作者: Ker, MD
Chuang, CH
Hsu, KC
Lo, WY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2002
摘要: A substrate-triggered technique is proposed to improve ESD Protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased similar to 65% by this substrate-triggered design.
URI: http://hdl.handle.net/11536/18869
ISBN: 0-7695-1562-2
期刊: PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN
起始頁: 331
結束頁: 336
Appears in Collections:Conferences Paper