| 標題: | A low-power 1.2GHz 0.35um CMOS PLL |
| 作者: | Juang, DC Chen, DS Shyu, JM Wu, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 2000 |
| 摘要: | In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35um TSMC CMOS technology. The total power consumption is 9.6mW at 1.2-GHz operating frequency with 1.5V supply voltage. The phase noise is -94dBc at 10KHz offset. |
| URI: | http://hdl.handle.net/11536/19327 |
| ISBN: | 0-7803-6470-8 |
| 期刊: | PROCEEDINGS OF THE SECOND IEEE ASIA PACIFIC CONFERENCE ON ASICS |
| 起始頁: | 99 |
| 結束頁: | 102 |
| 顯示於類別: | 會議論文 |

