完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Chen, TY | en_US |
dc.date.accessioned | 2014-12-08T15:41:07Z | - |
dc.date.available | 2014-12-08T15:41:07Z | - |
dc.date.issued | 2003-04-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2003.812495 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/27983 | - |
dc.description.abstract | The substrate triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as,comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits tor the input, output, and power pins have been designed and verified in a 0.18-mum salicided CMOS process. The experimental results have confirmed that the proposed substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices. The humari-body-model (HUM) ESD robustness of NMOS with a device dimension of W/L = 300 mum/0.3 mum can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV with the proposed substrate-triggered design. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | electrostatic discharge (ESD) | en_US |
dc.subject | ESD protection circuits | en_US |
dc.subject | gate-driven technique | en_US |
dc.subject | second breakdown | en_US |
dc.subject | substrate-triggered technique | en_US |
dc.title | Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2003.812495 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 50 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 1050 | en_US |
dc.citation.epage | 1057 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000183821800028 | - |
dc.citation.woscount | 10 | - |
顯示於類別: | 期刊論文 |