標題: Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism
作者: Kang, TK
Chen, MJ
Liu, CH
Chang, YJ
Fan, SK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: flash;gated-diode;inelastic tunneling;MOSFET;oxide breakdown;percolation;SILC;stress-induced leakage current;trap-assisted tunneling
公開日期: 1-Oct-2001
摘要: This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time tau, the neutral electron trap density N-t, and the trap energy level E-t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N-t explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes tau of 4.0 x 10(-13) s and E-t of 3.4 eV. The extracted tau is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.
URI: http://dx.doi.org/10.1109/16.954471
http://hdl.handle.net/11536/29348
ISSN: 0018-9383
DOI: 10.1109/16.954471
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 48
Issue: 10
起始頁: 2317
結束頁: 2322
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