標題: Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
作者: Ker, MD
Wu, CY
Huang, CC
Chen, TY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jun-1998
摘要: A new multiple-cell square-type layout design is proposed to realize the large-dimension output transistors for submicron low-voltage CMOS ICs. By using this layout design, the layout area of CMOS output buffers can be effectively reduced 30-40% with respect to the traditional finger-type layout. The drain-to-bulk parasitic capacitance of the output transistors is also reduced 40% by this square-type layout. Experimental results in a 0.6 mu m CMOS process have shown that the maximum driving (sinking) capability per unit layout area of a CMOS output buffer realized by the proposed multiple-cell square-type layout is improved 54% (34%) more than that by the traditional finger-type layout. The human-body-model (machine-model) ESD robustness per unit layout area of the CMOS output buffer realized by the proposed multiple-cell square-type layout is increased 25.2% (17.3%) as comparing to that by the traditional finger-type layout. (C) 1998 Published by Elsevier Science Ltd. All rights reserved.
URI: http://hdl.handle.net/11536/32595
ISSN: 0038-1101
期刊: SOLID-STATE ELECTRONICS
Volume: 42
Issue: 6
起始頁: 1007
結束頁: 1014
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