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dc.contributor.authorLiang, HCen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:01:31Z-
dc.date.available2014-12-08T15:01:31Z-
dc.date.issued1997-09-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/43.658570en_US
dc.identifier.urihttp://hdl.handle.net/11536/357-
dc.description.abstractFor sequential circuit test pattern generation incorporating backward justification, we need to justify the values on pip-pops to activate and propagate fault effects, This takes much time when the values to be justified on flip-flops appear to be invalid states, Hence, it is desirable to know invalid states, either dynamically during the justification process or statically before proceeding to test generation. This paper proposes algorithms to identify, before test generation, invalid states for sequential circuits without reset states, The first algorithm explores all valid states from an unknown initial state to search the complete set of invalid states, The second algorithm finds the complete set of invalid states from searching the reachable states for each state, The third algorithm searches the invalid states which are required for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit, Experimental results on ISCAS benchmark circuits show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation, and it was shown that they improved test generation significantly in test generation time, fault coverage, and detection efficiency, especially for larger circuits and for those that were difficult to generate.en_US
dc.language.isoen_USen_US
dc.subjectinvalid statesen_US
dc.subjectsequential test generationen_US
dc.subjectVLSI testingen_US
dc.titleIdentifying invalid states for sequential circuit test generationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/43.658570en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume16en_US
dc.citation.issue9en_US
dc.citation.spage1025en_US
dc.citation.epage1033en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
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