應用於兆級序列傳輸系統之等化器技術

Abstract

在多媒體時代的今天，各種高速串列傳輸技術廣泛的使用在許多高效能的電子產品中。為了讓訊號經過各種傳輸通道破壞後可以保持一定的品質，等化器在高速串列傳輸的系統中扮演了重要的角色。根據信號處理的方式我們可以將等化器分成連續時間領域等化器跟離散時間領域等化器。 在本論文中，首先我們提出了一個操作在6 Gbps 的連續時間領域等化器。在等化電路的輸入端我們使用了一個準位平移電路來減少通道輸出端直流電壓準位漂移對等化器造成的影響。準位平移電路同時也提供低頻訊號的放大功能。為了減少在增加高頻放大率的同時對低頻訊號的抑制量，我們將等化電路設計成兩級串接的模式。我們提出的連續時間領域等化器在時脈訊號頻率3 GHz 可以提供13.87 dB 的補償。實做晶片使用聯電標準臨界電壓90 耐米互補式金氧半導體製程來製造。佈局之後的模擬結果，位於等化器輸出端的信號眼圖可以開至正負250 mV，而緩衝器的輸出端可以將信號眼圖張開到規格所定的正負300mV。電路總面積為0.49 × 0.49 mm2。在1.0 V 的操作電壓下，電路總功率為78.83 mW。 接著，我們對一個半速率的決策回授等化器電路架構[8]提出跳躍式係數更新方案以及乒乓係數更新方案。該電路結構擁有5筆過去的資料消除符號間干擾並且使用一個位元的猜測方法來紓解時間上得限制。係數更新的演算法是使用sign-sign LMS演算法。在跳躍式係數更新方案中，係數計算電路的操作頻率將會降低而且功率消耗也會減少。乒乓係數更新方案則是在每個資料路徑上省下一個用來計算錯誤量正負號的比較器。針對這兩個係數更新方案，我們執行許多不同條件的模擬並且整理決策回授等化器係數收斂時間的表現。希望能夠藉此得到設計電路時在規格的規範下選擇相關參數的方針，尤其是決策回授等化器係數收練的速度。

In the multi-media era, many high-speed serial link trarnsmission technologies are developed and are widely used for high performance modern electronic product. In order to maintain the data quality that will be attenuated by communication channel, the equalizer becomes an important component in the high-speed serial link system. Based on the type of data processing, the equalizer can be categoried into continuous-time equalizer and discrete-time equalizer. In this thesis, we first propose a continuous-time qualizer that operates at 6 Gbps. We take a level-shifter stage in the front of our proposed equalizer for minimizing the DC voltage level variation in the equalizer input and for providing the low-frequency gain in the proposed circuit. In the equalization block, we use two serial cascade stages to minimize the gain suppression at low frequency while to boost the gain in high frequency. The proposed equalizer can compensate 13.87 dB channel loss at clock frequency of 3 GHz. The test chip is fabricated in UMC 90 nm CMOS regular-Vt process. The post-layout simulation results show that the data eye in the output of equazlier stage is about ±250 mV, and the data eye in the output of buffer stage can reach ±300 mV that meets our specification. Total area of our proposed equalizer including pads is 0.49 × 0.49 mm2 and power consumption is 78.83 mW under 1.0 V supply voltage. Secondly, we propose a hopping coefficients update and ping-pong coefficients update schemes for a discrete-time half-rate DFE (Decision-feedback equalizer) architecture [8]. The architecture uses five taps to cancel the ISI (intersymbol-interference) effects and uses the speculation method to relax the timing constrain. The algorithm used for coefficients update is the sign-sign LMS (least-mean-square) algorithm. For the hopping update scheme, the operation frequency of coefficients update block can be reduced and the power can be saved. For ping-pong update scheme, we calculate the sign of error under different conditions in these two data paths. The ping-pong update scheme saves one comparator for calculating the sign of error in each data path. For these two update schemes, we run different conditions and summary the convergent performance. We get the guideline of choosing parameters in the proposed equalizer under some system specifications especially the speed of convergence.