應用於視訊系統之快速相位追蹤與高頻率倍數全數位式鎖相迴路

Abstract

在本論文中，我們提出一個快速相位追蹤的高頻率倍數全數位式鎖相迴路，此電路可應用於視訊系統中的時脈產生器，其主要功能是接收顯示卡發出的水平同步訊號，依據使用者設定的螢幕解析度，產生高頻像素時脈來擷取類比的視訊訊號資料。取樣點和資料的相位差直接影響到顯示畫面的品質，若是像素時脈的相位不穩定，則顯示畫面會閃爍或抖動。因此，如何在高頻率倍數下，及時的追蹤與補償相位誤差，是此電路設計的重點。 在提出的架構中，我們使用了三角積分調變器來改進數位控制震盪器的等效解析度，並且加入時間數位轉換器迴路來即時補償相位誤差，另外針對數位控制震盪器中可能發生的不預期的突波作分析和預防。我們使用標準元件庫來設計整個晶片，並利用合成軟體及自動佈局工具實現電路，最後以0.18微米1P5M標準CMOS製程來製作晶片。

In this thesis, a fast phase-tracking all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The phase error between sampling clock and video data affects the display image quality directly. If the phase of pixel clock is not stable, the display image will be glittering or jittering. Therefore, how to design a fast phase-tracking clock generator with large multiplication factor is the point of this thesis. In the proposed architecture, a sigma-delta modulator is used to enhance the equivalent digital-controlled oscillator resolution, and a time-to-digital converter loop is applied to compensate the phase error immediately, and the glitch of DCO is also analyzed and prevented. This chip is implemented with standard cell library by synthesis and auto place-and-route tools, and realized using 0.18□m 1P5M standard CMOS process.