标题: | 混合讯号前端积体电路应用于可携式生医讯号撷取系统 A CMOS Mixed-Signal Front-End IC for Portable |
作者: | 余介恩 林进灯 周志成 电控工程研究所 |
关键字: | 生理讯号;脑电图;截波稳定式仪表放大器;切换式电容低通滤波器;切换电容式可变增益讯号放大器;多级杂讯移频三角积分类比/数位转换器;Biomedical signal;chopper-stabilized instrumentation amplifier;switched-capacitor low-pass filter;switched-capacitor variable gain amplifier;MASH 2-1-1 tri-level ΣΔ ADC |
公开日期: | 2008 |
摘要: | 在人体所有的生理讯号中,其讯号振幅皆非常微弱,亦容易被受测者本身、量测环境及设备等因素所影响,故本论文提出适用于各种电生理讯号撷取之晶片设计。除了一般着重的低功率、低杂讯之外,同时提高共模讯号拒斥比(CMRR)与电源涟波拒斥比(PSRR),并将整体多通道前端电路整合实现在单一晶片上,不需要任何外接元件,除了兼具成本与晶片面积效益,亦可降低因复杂的接线对生理讯号在量测时所造成的干扰,使后端处理及分析的讯号品质能够更为精确。另外,在系统加入了数位控制介面,根据不同生理讯号的需求,利用数位讯号去控制选择所要的讯号放大倍率与系统频宽。 本论文所设计的生理讯号撷取晶片包含:截波稳定式仪表放大器(CHS-IA)、类比多工器、切换式电容低通滤波器(SC-LPF)、非重叠时脉产生器(Non-Overlapping Clock Generator) 、切换电容式可变增益讯号放大器(SC-VGA)及多级杂讯移频三角积分类比/数位转换器(MASH 2-1-1 tri-level ΣΔ ADC)等电路。整个电路设计使用TSMC 0.18μm CMOS 1P6M 制程技术来实现,而整体晶片面积为1.9198 × 1.9198 。由模拟结果显示,在频率1024Hz下,可获得讯杂比90 dB,16位元解析度的效能。在操作电压1.8V下,总消耗功率约998μA。 Due to properties of low-amplitude and non-stationary, most of biomedical signals are easily influenced by examined persons, measured environment, and electronic devices. A novel analog circuit design is proposed in this thesis, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the multi-channel mixed-signal front-end integrated circuit (MSFEIC) is designed. This circuit is realized into a single chip without any external component. It can not only reduce the number of outer components, but also enhance a better signal-to-noise ratio enormously. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the controllable digital interface is also designed and integrated into MSFEIC. In this thesis, MSFEIC design is composed of four chopper-stabilized instrumentation amplifiers (CHS-IA), a switched-capacitor variable gain amplifier (SC-VGA), a switched-capacitor low-pass filter (SC-LPF), a non-overlapping clock generator, and a cascaded 2-1-1 tri-level sigma-delta analog-to-digital converter (MASH 2-1-1 tri-level ΣΔ ADC). These circuits have been integrated into a single chip of the total area of 1.9198×1.9198mm2 by using TSMC 0.18μm CMOS Mixed-Signal RF General purpose MiM Al 1P6M 1.8&3.3V process. For the simulation results, the proposed chip can achieve 90 dB of SNR, 16-bit resolution at 1024Hz. The total power consumption is about 998□W under 1.8V supply. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079612596 http://hdl.handle.net/11536/41914 |
显示于类别: | Thesis |
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