內建抖動測試之低功率全數位鎖相迴路

Abstract

本論文提出新的頻率搜尋演算法以及低功率的架構來設計一個低功率的全數位鎖相迴路。在演算法方面，使用新的頻率搜尋演算法能使我們的全數位鎖相迴路在18個參考週期內完成相位鎖定。而在電路設計方面，使用新的架構來實現我們的電路可以使頻率比較器,相位偵測器以及增益產生器整合在一個電路之中。在論文中,我們亦提出一個新的低功率數位控制震盪器而其頻率震盪範圍為200到750萬赫茲。總體而言，我們所提出的全數位鎖相迴路具有快速鎖定，面積小以及低功率消耗的特性。

在量測方面，時脈抖動是鎖相迴路重要的參數之一，而此參數的量測通常需要額外的量測儀器。使用額外的儀器來量測此參數會造成訊號嚴重的失真，所以在本論文中，我們使用內建時脈抖動量測技術來量測時脈抖動。

本論文以TSMC 0.13um 1P8M CMOS 技術實現。供給電壓為1.2伏，總面積為200um X 100um。模擬結果顯示當數位控制震盪器頻率為560萬赫茲時，全數位鎖相迴路的相位抖動為161.4ps，而總功率消耗為1.7mW。

A new architecture and algorithm for the all digital phase-locked loop (ADPLL) with low power design is presented in this thesis. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator structure for low power is presented in this thesis and its frequency range is from 200 MHz to 750 MHz. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption.

Clock jitter is one of main issues for PLL and conventionally jitter measurement rely on the external equipment. But the external equipment distort the tested clock signal seriously, it is a good choice to measure jitter by Built-In Jitter Self Test technique. In this thesis, Built-In Jitter Self Test technique is used for jitter measurement.

The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 200um x 100um. The simulation results show that when the DCO operates at 560MHz, the jitter is 161.4ps and the total power consumption of ADPLL is 1.7mW.