應用多重區域條件式成組縮放法於快速傅利葉轉換處理器之面積最小化技術

Abstract

快速傅利葉轉換處理器是正交分頻多工系統的計算核心，並且在過去幾十年間可以找到許多研究資料。為了提升定字元長度傅利葉轉換處理器的訊號對量化雜訊比，動態縮放法在執行運算時適應性地決定其縮放行為以避免不必要的精確度流失。當訊號對量化雜訊比的要求提高時，傳統上是去增加字元長度以得到更高的精確度。然而增加字元長度在面積上會付出許多代價，再者，有時候其實並不需要將精確度提升這麼多去滿足要求。在這篇論文裡，我們提出了一個利用了條件式縮放法及成組縮放法的優點的動態縮放法。此方法擁有非常經濟地使用面積去提升訊號對量化雜訊比的能力而不只是單純地去增加字元長度。因此，此方法的目標是在滿足訊號對量化雜訊比的要求下得到最小化的快速傅利葉轉換處理器的面積。實驗結果顯示在最佳的情形下，我們的方法相較於原本的條件式縮放法可以對8192點的快速傅利葉轉換處理器省下約13% 的面積。

The Fast Fourier Transform (FFT) processor is the key component of OFDM-base systems, and many literatures of FFT can be found in the past decades. To improve the SQNR in fixed-wordlength FFT, dynamic scaling methods adaptively determine the scaling behavior in run time to avoid the unnecessary loss of data information. Traditionally, increasing the wordlength is the way to acquire higher precision if the SQNR constraint is tighter. However, the increased wordlength results in a large amount of area cost. Moreover, sometimes we do not have to increase SQNR so much to meet the constraint. In this thesis, we proposed a dynamic scaling scheme which utilizes the profits of conditional scaling method and block scaling method. Our approach has the ability to economize the usage of area rather than increase the wordlength for SQNR improvement and the target is to minimize the area of FFT under the SQNR constraint. Experimental results show that our approach can reduce the area cost by about 13% in the best case for 8192-point FFT as compared to the existing conditional scaling method.