單晶片網路系統平台設計最佳化之研究

Abstract

隨著系統晶片持續的成長，設計複雜度增加，降低設計時程是一個重要的課題。因此我們提出單晶片網路產生器、快速傅立葉轉換產生器、以及乘法產生器來降低設計所需時間。讓系統設計者可以快速的得知電路的特性，讓電路設計者可以得到一個良好的設計。

在本研究中，我們提出高效能單晶片網路系統。根據虛擬電路交換、使用專屬的通道、流量採用比重分配、管線匯流排，我們可以達到以下的特性：(1) 保證頻寬 (2) 節省記憶體使用 (3) 不會產生死結。此外我們還提出通訊導向的任務指派演算法。此演算法使用剖析驅動的策略，讓系統總處理能力最大化。因此實作了時間精準的網路模擬器用於分析網路流量。通訊競爭的資訊可以被分析，並且回饋到最佳化流程。在最佳化的流程中，把時間與空間的通訊競爭一起考慮，讓 系統的通訊競爭降到最低。此外由於頻寬能力有其極限，頻寬需求超出極限時，整個系統會被其極限所限制住。因此頻寬的需求會被考慮到。在此演算法中，考慮到通訊量以及通訊競爭的狀況。 相較於沒有考慮的狀況下，系統效能提昇20%。

此外，針對管線式快速傅立葉轉化器的字元長度最佳化提出混合式的方法。此方法使用快速統計分析以及精準模擬分析來達到加速最佳化的流程。發展出統計上的不同字元長度的錯誤模型用於此最佳化流程。此外，硬體相關的模型被抽取出來計算工作頻率，以達到使用者的頻率要求。在最佳化的過程中，根據使用者的限制，首先找出最佳解可能的範圍，還有最佳解的形式可以有效的降低最佳解的空間。此混合式方法相較於純粹的模擬分析可以有效的減少所需評估時間，相較於純粹的統計分析，可獲得更加精確的結果。

最後，一個有效率的合成演算法被提出用於乘法器的自動產生器。此合成演算法在非規則的樹狀合成問題上考慮到邏輯閘延遲以及繞線延遲。根據合成樹的到達時間以及應到時間的要求，可以平衡生成樹的路徑延遲。使用新穎的樹狀生成演算法，考慮到每一條路徑的延遲。所建構的合成器可以產生高速度以及小面積的乘法器。

As System-on-Chip (SoC) designs progressively grow, reducing the development time becomes a crucial challenge. Therefore, the Network-on-Chip (NoC) generator, the FFT generator, and the multiplier generator are developed for reducing the design time.

In this work, a high-performance Network-on-Chip platform is presented. To achieve (1) bandwidth guarantee (2) economical memory usage, and (3) deadlock free, the virtual-circuit switching with dedicated connection path, virtual channel flow control with weighted round-robin scheduling, and the pipelined bus are used. To perform the task binding, a communication-driven task binding algorithm is proposed. This algorithm employs profile-driven strategy to bind tasks onto the NoC such that the overall system throughput can be maximized. To analyze the network traffic, a cycle-accurate network simulator is hence implemented. The traffic contention information is analyzed, and then fed back to the proposed optimization flow. The effects of communication amount, traffic contention, and bandwidth requirement are considered to perform the task binding. The overall system throughput is improved up to 20% for 100 test cases as compared with the task binding without considering the communication and contention effects.

This thesis also describes a novel hybrid method for the wordlength optimization of pipelined FFT processors which is the arithmetic kernel of OFDM-based systems. This methodology utilizes the rapid computation of statistical analysis, and the accurate evaluation of simulation-based analysis to investigate a speedy optimization flow. A statistical error model for varying wordlengths of PE stages of an FFT processor is developed to support this optimization flow. A technology-dependent model is extracted to support the FFT's operating frequency constraint. The wordlength boundary is found by constraints, and the optimal form is introduced to reduce computation time. Experimental results show that the wordlength optimization employing the speedy flow reduces the percentage of the total area of the FFT processor that increases with an increasing FFT length. The proposed hybrid method requires shorter prediction time than the absolute simulation-based method does and achieves more accurate outcomes than a statistical calculation does.

Finally, an effective multiplier synthesis algorithm for cell-based multipliers is presented. The synthesis algorithm considers gate delay and wire delay for non-regular tree synthesis. Based on arrival time and required time of the tree constraints, the generated compressed tree can achieve balanced path delay. By using a novel tree generation algorithm with timing consideration for each vertical compressor slice (VCS), the developed synthesizer can automatically generate high-speed multipliers in small area.