深次微米 CMOS 製程技術以避免電栓鎖定之分析與模擬

Abstract

在互補式金氧半結構中，寄生雙載子電晶體所引發的電栓鎖定是個嚴重問 題， 尤其在極大型積體電路而言。本論文用模擬軟體找出其特性，由模 擬結果可知其可靠度進而改善元件製程和設計，並且可預測元件特性。在 各種改良結構中，我們將著重於溝槽隔離，保護環，反擴散分佈井和淺接 合面。而根據一些模擬結果可簡單得知元件是否可靠，免去昂貴又耗時的 實驗過程。淺溝槽隔離在極大型積體電路中可能取代其它隔離技術，因為 它不形成鳥嘴且完全平面化，而深溝槽隔離雖在製程上較複雜但效果不錯 ，保護環和磊晶一起使用可完全消除電栓鎖定，而由模擬軟體能得知保護 環理想寬度該用多少，反擴散分佈井則不必多用晶片面積，可做到高密度 。淺接合面也很省面積而且減少了高能量離子佈植這一步驟，反擴散分佈 井則常使用高達數十萬電子伏特的能量。以上這些技術及結構皆可避免電 栓鎖定。 Latchup in CMOS parasitic bipolar transistor is a critical problem for the ULSI era. In this thesis, we use simulation tool to show the characteristics. From simulation results, we can know some information about reliability, then improve their process and design. Furthermore, we can predict devices' characteristics. According to the simulation results, we can simply find out the latchup susceptibility of designed devices without expensive and long-time experiment.Trench isolation is likely to replace other isolation techniques in future CMOS technology since trench is planar with silicon surface and has no bird's beak.Guard ring with epitaxial layer can totally eliminate latchup. As shown in this thesis, a proper width can be determined in N-well guard ring. Retrograde well does not use too much wafer area so it can be used in high density chips. Shallow junction formation saves area too. And it does not need high energy implantation. However, retrograde well often needs high energy implantation. The technologies and structures stated above can prevent latchup.