標題: | Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness |
作者: | Lin, Horng-Chih Chen, Wei-Chen Lin, Chuan-Ding Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Double gate;nanowire (NW);polycrystalline silicon (poly-Si) |
公開日期: | 1-Jun-2009 |
摘要: | A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously. |
URI: | http://dx.doi.org/10.1109/LED.2009.2018493 http://hdl.handle.net/11536/7160 |
ISSN: | 0741-3106 |
DOI: | 10.1109/LED.2009.2018493 |
期刊: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 30 |
Issue: | 6 |
起始頁: | 644 |
結束頁: | 646 |
Appears in Collections: | Articles |
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