標題: 以二維加-比較-選擇結構為基礎的高速維特比解碼器
High-Speed Viterbi Decoder Based on the Two-Dimensional ACS Structure
作者: 陳志龍
Chih-Lung Chen
李鎮宜
Chen-Yi Lee
電子研究所
關鍵字: 維特比;加-比較-選擇;高速;時序重訂;Viterbi;ACS;high-speed;retiming
公開日期: 2005
摘要: 本論文提出一個利用高基數籬笆圖結構的高速維特比解碼器。我們提出二維的加-比較-選擇單元可以使高基數維特比解碼器具有更佳的成本效益。此外,可以進一步利用資料路徑的時序重訂來提高解碼速度。論文中介紹通用的時序重訂方法以及二維加-比較-選擇單元的架構,同時藉由實現64狀態的維特比解碼器來驗證提出的方法。根據實驗結果,此解碼器在0.13μm製程下最高能達到1.1Gb/s的傳輸速度,晶片的面積是1.96mm^2。此外,在MB-OFDM UWB系統規範最高傳輸速度480Mb/s下,解碼晶片的最小面積為0.9mm^2。
A high-speed Viterbi decoder based on the high-radix trellis structures is presented. The proposed two-dimensional add-compare-select unit can result in much cost efficient design for a high-radix Viterbi decoder. Moreover, the decoding speed can be further enhanced through datapath retiming. The general retiming approach and the two-dimensional architecture are introduced, and the implementation of a 64-state Viterbi decoder is reported to verify the proposed methods. The simulation results indicate the present decoder can provide the maximum 1.1 Gb/s throughput in the 1.96 mm^2 0.13-μm silicon area. Furthermore, the smallest decoder chip in supporting the multiband orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband system has an area of 0.9mm^2.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311620
http://hdl.handle.net/11536/78089
Appears in Collections:Thesis


Files in This Item:

  1. 162001.pdf
  2. 162002.pdf
  3. 162003.pdf
  4. 162004.pdf
  5. 162005.pdf
  6. 162006.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.