標題: An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
作者: Hsu, TY
Shieh, BJ
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: all-digital phase-locked loop (ADPLL);clock recovery;frequency synthesizer;phase-locked loop
公開日期: 1-Aug-1999
摘要: A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell, These modules have been designed and verified on a 0.6-mu m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clack generator can generate any target clock rate f(clock); and 3) the function of nonreturn-to-zero clock recovery has a maximum f(clock)/4 recovering capability vith a locking range of (tau(input) + tau(input)/2), where tau(input) is the input period.
URI: http://dx.doi.org/10.1109/4.777104
http://hdl.handle.net/11536/31194
ISSN: 0018-9200
DOI: 10.1109/4.777104
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 34
Issue: 8
起始頁: 1063
結束頁: 1073
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