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dc.contributor.author賴明秀en_US
dc.contributor.authorMing-Hsiu Laien_US
dc.contributor.author陳紹基en_US
dc.contributor.authorDr. Sau-Gee Chenen_US
dc.date.accessioned2014-12-12T01:35:09Z-
dc.date.available2014-12-12T01:35:09Z-
dc.date.issued2003en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009111605en_US
dc.identifier.urihttp://hdl.handle.net/11536/43691-
dc.description.abstract極高位元率數位用戶迴路 (VDSL) 為近來最新發展xDSL傳輸技術, 可藉由電話線路提供高速資料傳輸。對VDSL系統而言,離散多音頻 (DMT) 為一廣受青睞之多載波調變技術。由於大量的次載波數目和高密度的星座圖,使離散多音頻調變之系統對於同步所產生的誤差非常敏感。本文中,我們提出一個適用於美國ANSI T1E1.4 VDSL 標準之同步程序以及一個基於訊號內插的取樣誤差修正方式。同步程序中要完成之工作包括:符元同步、取樣時間誤差粗調、通道估計及等化、取樣時間誤差細調。我們先用一個簡單的相關器進行符元同步偵測,然後在頻域利用某些己知資料得到取樣時間誤差,調整後便可以進行通道估測及補償。在結合頻域等化器 (FEQ) 以補償不完美的內插器之頻率響應狀況下,我們發現Cubic B-spline 內插器可得到極佳的效能同時又具有極低之運算複雜度。zh_TW
dc.description.abstractVery high bite rate digital subscriber lines (VDSL) is the latest xDSL transmission system for carrying high speed data over telephone lines. Discrete multi-tone (DMT) is a popular multi-carrier modulation technique for VDSL. DMT-based system is very sensitive to synchronization errors due to its high number of sub-carriers and involved high-density constellation. In this work, we propose a synchronization procedure for the ANSI T1E1.4 VDSL standard and a sample timing correction scheme based on signal interpolation. The proposed synchronization procedure includes symbol synchronization, sampling timing acquisition, channel estimation and sampling timing tracking. Symbol synchronization is first done by a simple correlator. Sampling timing error is obtained by some pilot data in frequency domain. As soon as the sampling timing error is compensated, channel estimation and equalization can be easily done. By combining frequency-domain equalizers (FEQ) which can compensate frequency distortion due to interpolation filters, we found that the Cubic B-spline interpolator yields excellent performance with low computational complexity.en_US
dc.language.isoen_USen_US
dc.subject同步zh_TW
dc.subjectVDSL系統zh_TW
dc.subjectDMTen_US
dc.subjectVDSLen_US
dc.subjectclock offseten_US
dc.subjectsynchronizationen_US
dc.title極高位元率數位用戶迴路之時脈同步設計zh_TW
dc.titleClock Synchronization of VDSL Systemen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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  2. 160502.pdf
  3. 160503.pdf
  4. 160504.pdf
  5. 160505.pdf
  6. 160506.pdf
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  8. 160508.pdf
  9. 160509.pdf
  10. 160510.pdf

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