標題: Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions
作者: Lin, S. H.
Cheng, C. H.
Chen, W. B.
Yeh, F. S.
Chin, Albert
機械工程學系
電子工程學系及電子研究所
Department of Mechanical Engineering
Department of Electronics Engineering and Institute of Electronics
關鍵字: LaTiO;low V(t);solid-phase diffusion (SPD)
公開日期: 1-Jun-2009
摘要: We demonstrate a low threshold voltage (V,) of -0.17 V and good hole mobility (54 cm(2)/V (.) s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.
URI: http://dx.doi.org/10.1109/LED.2009.2020307
http://hdl.handle.net/11536/7162
ISSN: 0741-3106
DOI: 10.1109/LED.2009.2020307
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 30
Issue: 6
起始頁: 681
結束頁: 683
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